公开(公告)号：US20190295669A1

公开(公告)日：2019-09-26

申请号：US15928976

申请日：2018-03-22

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Piyush Dak ,  Wei Zhao ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Mohan Dunga

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programing operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.

公开(公告)号：US10381083B1

公开(公告)日：2019-08-13

申请号：US16018018

申请日：2018-06-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kun-Huan Shih ,  Matthias Baenninger ,  Huai-Yuan Tseng ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/24 ,  G11C16/30 ,  G11C16/08 ,  G11C16/34 ,  H01L27/1157 ,  G11C16/04 ,  H01L27/11524

Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel potential gradient near the select gate transistors is reduced when the voltages of the bit line and the substrate are suitably controlled. In one approach, the voltage of the substrate at a source end of the memory string is increased to an intermediate level first before being increased to the erase voltage threshold level while the voltage of the bit line is held at a reference voltage level to delay floating the voltage of the bit line. Another approach builds off the first approach by temporarily decreasing the voltage of the bit line to a negative level before letting the voltage of the bit line to float at the same time as the voltage of the substrate is increased to the erase voltage threshold level.

公开(公告)号：US10229744B2

公开(公告)日：2019-03-12

申请号：US15816546

申请日：2017-11-17

Applicant: SanDisk Technologies LLC

Inventor： Deepanshu Dutta ,  Idan Alrod ,  Huai-Yuan Tseng ,  Amul Desai ,  Jun Wan ,  Ken Cheah ,  Sarath Puthenthermadam

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/16 ,  G11C8/08 ,  G11C16/08 ,  G11C29/02 ,  G11C11/56 ,  G11C29/12

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.

公开(公告)号：US10026486B1

公开(公告)日：2018-07-17

申请号：US15451186

申请日：2017-03-06

Applicant: SanDisk Technologies LLC

Inventor： Deepanshu Dutta ,  Idan Alrod ,  Huai-Yuan Tseng ,  Amul Desai ,  Jun Wan ,  Ken Cheah ,  Sarath Puthenthermadam

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/16

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.