Abstract:
An interface system including: a receiver; a transmitter configured to transmit a signal including a common mode voltage to the receiver through transmission lines; and a plurality of bias circuits configured to adjust the common mode voltage of the signal, wherein the bias circuits are configured to receive a bias control bit to generate a biased common mode voltage.
Abstract:
A display device includes: a gain provider configured to set a time point elapsed by a set period from a time point at which a first region of an input image is detected as a still region, as a set time, and to gradually decrease a gain value from the set time; and a grayscale converter configured to generate an output image by applying the gain value to the first region and a second region including a peripheral region of the first region among the input image, wherein the gain provider is configured to set the set period differently according to size of grayscale values in the first region.
Abstract:
A display device includes: a display panel including a plurality of pixels; a power supply configured to generate a gamma power voltage based on a power control signal; a gamma voltage generator configured to generate gamma voltages based on the gamma power voltage and a gamma control signal; a data driver configured to generate a data signal corresponding to a grayscale value included in image data using the gamma voltages and to provide the data signal to the pixels; and a power controller configured to adjust the power control signal and the gamma control signal based on a maximum voltage level of the data signal, wherein a voltage level of the gamma power voltage is proportional to the maximum voltage level of the data signal.
Abstract:
A source driver includes an equalizer which outputs compensated image data by adjusting a frequency gain of image data, based on a selected option value among a plurality of option values. A recovery recovers a clock signal corresponding to the compensated image data. A calibrator sequentially provides the plurality of option values to the equalizer, and selects the selected option value among the plurality of option values, based on recovery rates of the clock signal, which respectively correspond to the plurality of option values.
Abstract:
A driving voltage provider includes: a PLL circuit for generating clock signals with different phases according to a divider value; a DC-DC converter for generating a PWM signal according to the frequency of a first clock signal, and providing a driving voltage based on the duty ratio of the PWM signal; a first tuning circuit for outputting a first tuning signal having a first logic level when the logic levels of first and second sampling signals obtained by sampling the PWM signal at transition times of different clock signals are different, and outputting the first tuning signal having a second logic level when the first and second sampling signals have the same logic level; and a divider value determiner for decreasing the divider value when the logic level of the first tuning signal is the first logic level.
Abstract:
An image correcting unit including: a data converting unit which receives image data, and generates display data by converting respective grayscale values which are included in the image data to high pixel data and low pixel data; and a white pixel detecting unit which detects image data lines which include not less than a first number of white grayscale values from the image data, and outputs a conversion signal when not less than a second number of the detected image data lines are successively arranged, wherein upon receiving the conversion signal from the white pixel detecting unit, the data converting unit converts the white grayscale values which are included in the successively arranged image data lines to first high pixel data and first low pixel data, wherein the first high pixel data and the first low pixel data have a different value from each other.
Abstract:
There is provided a display device including an input unit configured to connect an external device to a serial peripheral interface (SPI) through a plurality of connection lines, a switching unit configured to connect the input unit and a flash memory of a driving board to the SPI, a data register configured to output connection setting data for determining a connection state of the switching unit, and a timing controller configured to output a control signal for determining the connection setting data according to an input of a write enable line among the plurality of connection lines.
Abstract:
A power supply of the present disclosure includes: a power generator that generates a first driving voltage to be supplied to a timing controller; and a voltage compensator that performs feedback of the first driving voltage and generates a feedback voltage according to a voltage difference between the first driving voltage and a first reference voltage supplied from the power generator. In this structure, the power generator generates a second driving voltage by boosting or dropping the first driving voltage to correspond to the feedback voltage, and may supply the second driving voltage to the timing controller.
Abstract:
A method of reducing a time for switching a gate line driving signal of display device having plural gate lines from a level that is less than a full gate-on level to the gate-on level is disclosed. The method may include: during a gate line pre-charging period of a respective gate line, causing the gate line driving signal to be at the full gate-on level; during a corresponding gate line main-charging period that follows the pre-charging period, causing the gate line driving signal of to be at the full gate-on level; and during an interposed period that is interposed between the gate line pre-charging period and its corresponding gate line main-charging period, causing the gate line driving signal to be at an intermediate level that is between the full gate-on level and an opposed gate-off level.