公开(公告)号：US11321268B2

公开(公告)日：2022-05-03

申请号：US14530266

申请日：2014-10-31

Applicant: Texas Instruments Incorporated

Inventor： David M. Thompson ,  Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

IPC: G06F13/362 ,  G06F13/42

Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.

公开(公告)号：US20210406021A1

公开(公告)日：2021-12-30

申请号：US17472852

申请日：2021-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/30 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/345 ,  G06F11/00 ,  G06F12/02

Abstract: A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

公开(公告)号：US20210390018A1

公开(公告)日：2021-12-16

申请号：US17408561

申请日：2021-08-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F11/10 ,  G06F11/14 ,  G06F9/345 ,  G06F12/0817 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/38 ,  G06F11/00

Abstract: Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

公开(公告)号：US11113057B2

公开(公告)日：2021-09-07

申请号：US16808653

申请日：2020-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/312 ,  G06F11/00 ,  G06F12/08 ,  G06F9/30 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/0811 ,  G06F9/345 ,  G06F11/10

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.

公开(公告)号：US11106463B2

公开(公告)日：2021-08-31

申请号：US16421920

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Zbiciak ,  Kai Chirca

IPC: G06F9/30

Abstract: A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

公开(公告)号：US10936317B2

公开(公告)日：2021-03-02

申请号：US16422324

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Zbiciak ,  Sahithi Krishna ,  Soujanya Narnur

IPC: G06F12/02 ,  G06F9/30 ,  G06F12/0811

Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

公开(公告)号：US10908901B2

公开(公告)日：2021-02-02

申请号：US15636669

申请日：2017-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/34 ,  G06F12/0875

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Upon a stream break instruction specifying one of the nested loops, the stream engine ends a current iteration of the loop. If the specified loop was not the outermost loop, the streaming engine begins an iteration of a next outer loop. If the specified loop was the outermost nested loop, the streaming engine ends the stream. The streaming engine places a vector of data elements in order in lanes within a stream head register. A stream break instruction is operable upon a vector break.

公开(公告)号：US20210026776A1

公开(公告)日：2021-01-28

申请号：US17067986

申请日：2020-10-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F12/0897 ,  G06F9/30 ,  G06F12/0815 ,  G06F12/0875 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0862

Abstract: A streaming engine employed in a digital data processor may specify a fixed read-only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register independently specifies a linear address or a circular address mode for each of the nested loops.

公开(公告)号：US10810131B2

公开(公告)日：2020-10-20

申请号：US16437900

申请日：2019-06-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/355 ,  G06F12/04 ,  G06F12/0897 ,  G06F9/30 ,  G06F12/0815 ,  G06F12/0875 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0862

Abstract: A streaming engine employed in a digital data processor may specify a fixed read-only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register independently specifies a linear address or a circular address mode for each of the nested loops.

公开(公告)号：US10747636B2

公开(公告)日：2020-08-18

申请号：US16112996

申请日：2018-08-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D Anderson ,  Duc Bui ,  Kai Chirca

IPC: G06F9/34 ,  G06F11/00 ,  G06F12/08 ,  G06F13/38 ,  G06F11/30 ,  G06F12/0875 ,  G06F12/0862 ,  G06F11/27 ,  G06F13/16 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/36 ,  G06F11/07 ,  G06F11/10

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.