公开(公告)号：US09489307B2

公开(公告)日：2016-11-08

申请号：US14031390

申请日：2013-09-19

Applicant: Texas Instruments Incorporated

Inventor： Daniel B Wu ,  Timothy D Anderson

IPC: G06F13/40 ,  G06F12/08 ,  G06F13/16

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The powerdown mechanism is isolated to just the asynchronous bridge implemented between the master and the interconnect with a basic request/acknowledge handshake between the master subsystem and the asynchronous bridge.

Abstract translation: 在高速缓存一致主机和相干系统互连之间实现异步双域网桥。 该桥具有两个半部分，每个时钟/电源下降域主和互连中一个。 掉电机制与主站和互连之间实现的异步桥隔离，主站与异步桥之间的基本请求/确认握手。

公开(公告)号：US10037439B2

公开(公告)日：2018-07-31

申请号：US14062002

申请日：2013-10-24

Applicant: Texas Instruments Incorporated

Inventor： Timothy D Anderson ,  Joseph R. M. Zbiciak ,  Matthew D Pierson ,  Kai Chirca

IPC: G06F21/78 ,  G06F12/0815 ,  G06F21/79 ,  G06F12/14 ,  G06F12/0831 ,  G06F13/16 ,  H04L29/06 ,  G06F13/42 ,  G06F12/0817 ,  G06F12/1081 ,  G06F13/28 ,  G06F13/40 ,  G06F12/0842

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention is a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.

公开(公告)号：US20160055096A1

公开(公告)日：2016-02-25

申请号：US14931406

申请日：2015-11-03

Applicant: Texas Instruments Incorporated

Inventor： Kai Chirca ,  Matthew D Pierson ,  Daniel B Wu ,  Timothy D Anderson

IPC: G06F12/10 ,  G06F13/40 ,  G06F13/28 ,  G06F12/08

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.

Abstract translation: 本发明结合了多核共享存储器控制器和异步协议转换桥以创建非常有效的异构多处理器系统。 在通过协议转换网桥之后，命令行进通过常规处理器端口。 这允许互连保持不变，同时连接不同处理器的任何组合。 本发明将所有处理器紧密地集成到相同的存储器控​​制器/互连中。

公开(公告)号：US09152586B2

公开(公告)日：2015-10-06

申请号：US14056775

申请日：2013-10-17

Applicant: Texas Instruments Incorporated

Inventor： Daniel B Wu ,  Matthew D Pierson ,  Kai Chirca ,  Timothy D Anderson

IPC: G06F13/16 ,  G06F13/40 ,  G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

Abstract translation: 为了能够有效跟踪事务，使用确认期望信号来给缓存一致互连提供一个交易是否需要连贯的所有权跟踪的提示。 该信号通知高速缓存相干互连，以便在读/写传输完成时期望来自发起主机的所有权转移确认信号。 因此，高速缓存相干互连可以在其一致性点继续跟踪事务，直到在必要时从发起主机接收到确认。

公开(公告)号：US09372799B2

公开(公告)日：2016-06-21

申请号：US14841956

申请日：2015-09-01

Applicant: Texas Instruments Incorporated

Inventor： Daniel B Wu ,  Matthew D Pierson ,  Kai Chirca ,  Timothy D Anderson

IPC: G06F13/00 ,  G06F12/08 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

公开(公告)号：US09129071B2

公开(公告)日：2015-09-08

申请号：US14057205

申请日：2013-10-18

Applicant: Texas Instruments Incorporated

Inventor： Matthew D Pierson ,  Kai Chirca ,  Timothy D Anderson

IPC: G06F12/08 ,  G06F13/42 ,  G06F13/16 ,  H04L29/06

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention speeds operation for coherence writes to shared memory. This invention immediately commits to the memory endpoint coherence write data. Thus this data will be available earlier than if the memory controller stalled this write pending snoop responses. This invention computes write enable strobes for the coherence write data based upon the cache dirty tags. This invention initiates a snoop cycle based upon the address of the coherence write. The stored write enable strobes enable determination of which data to write to the endpoint memory upon a cached and dirty snoop response.

Abstract translation: 本发明加速了对共享存储器的一致性写操作。 本发明立即提交到存储器端点一致写入数据。 因此，如果内存控制器停止了这个写入挂起的侦听响应，那么这个数据将可用。 本发明基于高速缓存脏标签计算用于相干写入数据的写入使能选通。 本发明基于一致性写入的地址启动窥探循环。 存储的写使能选通使得能够确定在高速缓存和脏的窥探响应时哪些数据写入端点存储器。

公开(公告)号：US20140115266A1

公开(公告)日：2014-04-24

申请号：US14056775

申请日：2013-10-17

Applicant: Texas Instruments Incorporated

Inventor： Daniel B Wu ,  Matthew D Pierson ,  Kai Chirca ,  Timothy D Anderson

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

Abstract translation: 为了能够有效跟踪事务，使用确认期望信号来给缓存一致互连提供一个交易是否需要连贯的所有权跟踪的提示。 该信号通知高速缓存相干互连，以便在读/写传输完成时期望来自发起主机的所有权转移确认信号。 因此，高速缓存相干互连可以在其一致性点继续跟踪事务，直到在必要时从发起主机接收到确认。

公开(公告)号：US10747636B2

公开(公告)日：2020-08-18

申请号：US16112996

申请日：2018-08-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D Anderson ,  Duc Bui ,  Kai Chirca

IPC: G06F9/34 ,  G06F11/00 ,  G06F12/08 ,  G06F13/38 ,  G06F11/30 ,  G06F12/0875 ,  G06F12/0862 ,  G06F11/27 ,  G06F13/16 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/36 ,  G06F11/07 ,  G06F11/10

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

公开(公告)号：US09465767B2

公开(公告)日：2016-10-11

申请号：US14931406

申请日：2015-11-03

Applicant: Texas Instruments Incorporated

Inventor： Kai Chirca ,  Matthew D Pierson ,  Daniel B Wu ,  Timothy D Anderson

IPC: G06F15/00 ,  G06F13/42 ,  G06F12/08 ,  G06F13/16 ,  H04L29/06 ,  G06F1/12

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.