公开(公告)号：US20220367703A1

公开(公告)日：2022-11-17

申请号：US17869163

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Pei-Hsun Wang ,  Lo-Heng Chang ,  Jung-Hung Chang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.

公开(公告)号：US20220344213A1

公开(公告)日：2022-10-27

申请号：US17238376

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Kuan-Ting Pan ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Chien Ning Yao

IPC: H01L21/8234 ,  H01L29/786 ,  H01L29/423

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

公开(公告)号：US20220336452A1

公开(公告)日：2022-10-20

申请号：US17856471

申请日：2022-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Huan-Chieh Su ,  Zhi-Chang Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/033 ,  H01L21/8234

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

公开(公告)号：US11450754B2

公开(公告)日：2022-09-20

申请号：US16872058

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Lo-Heng Chang ,  Jung-Hung Chang ,  Kuo-Cheng Chiang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423

Abstract: Semiconductor devices using a dielectric structure and methods of manufacturing are described herein. The semiconductor devices are directed towards gate-all-around (GAA) devices that are formed over a substrate and are isolated from one another by the dielectric structure. The dielectric structure is formed over the fin between two GAA devices and cuts a gate electrode that is formed over the fin into two separate gate electrodes. The two GAA devices are also formed with bottom spacers underlying source/drain regions of the GAA devices. The bottom spacers isolate the source/drain regions from the substrate. The dielectric structure is formed with a shallow bottom that is located above the bottoms of the bottom spacers.

公开(公告)号：US20220181490A1

公开(公告)日：2022-06-09

申请号：US17682739

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hung Chang ,  Lo-Heng Chang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

Abstract: A method of independently forming source/drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source/drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source/drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source/drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source/drain region, the second inner spacer layer comprising a second material different from the first material.

公开(公告)号：US11328963B2

公开(公告)日：2022-05-10

申请号：US16947398

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Huan-Chieh Su ,  Zhi-Chang Lin ,  Shi Ning Ju ,  Yi-Ruei Jhan ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311

Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

公开(公告)号：US11322493B2

公开(公告)日：2022-05-03

申请号：US16929592

申请日：2020-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Huan-Chieh Su ,  Kuo-Cheng Chiang

IPC: H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/786

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

公开(公告)号：US11264485B2

公开(公告)日：2022-03-01

申请号：US16662333

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Han Wang ,  Ding-Kang Shih ,  Chun-Hsiung Lin ,  Teng-Chun Tsai ,  Zhi-Chang Lin ,  Akira Mineji ,  Yao-Sheng Huang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.

公开(公告)号：US20210391477A1

公开(公告)日：2021-12-16

申请号：US16898717

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lo-Heng Chang ,  Jung-Hung Chang ,  Zhi-Chang Lin ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes forming a fin of alternating layers of semiconductor nanostructures and sacrificial layers, laterally etching sidewall portions of the sacrificial layers, and depositing additional semiconductor material over the sidewalls of the semiconductor nanostructures and sacrificial layers. Following deposition of a dielectric material over the additional semiconductor material and additional etching, the remaining portions of the semiconductor structures and additional semiconductor material collectively form a hammer shape at each opposing side of the fin. Epitaxial source/drain regions formed on the opposing sides of the fin will contact the heads of the hammer shapes.

公开(公告)号：US20210391423A1

公开(公告)日：2021-12-16

申请号：US16901919

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Lo-Heng Chang

IPC: H01L29/08 ,  H01L29/66

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises alternately forming first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers include different materials and are stacked up along a direction substantially perpendicular to a top surface of the substrate; forming a dummy gate structure over the first and second semiconductor layers; forming a source/drain (S/D) trench along a sidewall of the dummy gate structure; forming inner spacers between edge portions of the first semiconductor layers, wherein the inner spacers are bended towards the second semiconductor layers; and epitaxially growing a S/D feature in the S/D trench, wherein the S/D feature contacts the first semiconductor layers and includes facets forming a recession away from the inner spacers.