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    Buried SiGe oxide FinFET scheme for device enhancement
    84.
    发明授权
    Buried SiGe oxide FinFET scheme for device enhancement 有权
    埋地SiGe氧化物FinFET方案用于器件增强

    公开(公告)号：US09202917B2

    公开(公告)日：2015-12-01

    申请号：US13952753

    申请日：2013-07-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Zhiqiang Wu ,  Gwan Sin Chang

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7849

    Abstract: The present disclosure relates to a Fin field effect transistor (FinFET) device having a buried silicon germanium oxide structure configured to enhance performance of the FinFET device. In some embodiments, the FinFET device has a three-dimensional fin of semiconductor material protruding from a substrate at a position located between first and second isolation regions. A gate structure overlies the three-dimensional fin of semiconductor material. The gate structure controls the flow of charge carriers within the three-dimensional fin of semiconductor material. A buried silicon-germanium-oxide (SiGeOx) structure is disposed within the three-dimensional fin of semiconductor material at a position extending between the first and second isolation regions.

    Abstract translation: 本公开涉及具有被配置为增强FinFET器件的性能的掩埋硅锗氧化物结构的Fin场效应晶体管（FinFET）器件。 在一些实施例中，FinFET器件具有在位于第一和第二隔离区域之间的位置处从衬底突出的半导体材料的三维鳍。 栅极结构覆盖半导体材料的三维鳍。 栅极结构控制半导体材料的三维鳍内的电荷载流子的流动。 掩埋的硅 - 锗氧化物（SiGeOx）结构设置在半导体材料的三维翅片内，在第一和第二隔离区域之间延伸的位置。

    TRANSISTOR DESIGN
    85.
    发明申请
    TRANSISTOR DESIGN 有权
    晶体管设计

    公开(公告)号：US20150200253A1

    公开(公告)日：2015-07-16

    申请号：US14156546

    申请日：2014-01-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Yuan Chen ,  Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Zhiqiang Wu

    IPC: H01L29/10 ,  H01L29/66 ,  H01L29/417 ,  H01L29/167 ,  H01L29/16 ,  H01L29/165 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/36

    CPC classification number: H01L29/1054 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

    Abstract: Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel. In some embodiments, a counter-doped layer underlies the delta-doped layer configured to reduce leakage within the semiconductor substrate, and includes dopant impurities of a second impurity type, which is opposite the first impurity type.

    Abstract translation: 本公开的一些实施例涉及形成在包含第一杂质类型的掺杂杂质的半导体衬底中的晶体管器件。 该晶体管器件包括由包括第一杂质类型的掺杂杂质的δ掺杂层构成的沟道，并且被配置为在沟道内产生峰值掺杂剂浓度。 通道还包括覆盖在δ掺杂层上的含碳材料层，并且被配置为防止掺杂剂从δ-掺杂层和半导体衬底的反向扩散。 通道还包括覆盖在含碳材料层上的衬底材料层，并且被配置为在通道的表面附近实现陡峭的逆向掺杂剂浓度分布。 在一些实施例中，反掺杂层位于配置成减少半导体衬底内的泄漏的δ掺杂层的下面，并且包括与第一杂质类型相反的第二杂质类型的掺杂杂质。

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