公开(公告)号：US08513716B2

公开(公告)日：2013-08-20

申请号：US13016481

申请日：2011-01-28

申请人： Yoshitaka Ueda ,  Kouichi Yamada ,  Atsushi Wada ,  Shigeto Kobayashi

发明人： Yoshitaka Ueda ,  Kouichi Yamada ,  Atsushi Wada ,  Shigeto Kobayashi

IPC分类号： H01L29/78

CPC分类号： H01L27/105

摘要： A MOS transistor includes a gate electrode formed in a grid pattern, source regions and drain regions each surrounded by the gate electrode, and a source metal wiring connected to the source regions via source contacts and a drain metal wiring connected to the drain regions via drain contacts. The source metal wiring and the drain metal wiring are disposed along one direction of the grid of the gate electrode. Each of the source regions and the drain regions is a rectangular form having its long side along the length direction of each metal wiring. The source metal wiring and the drain metal wiring are each formed in a zigzag manner in the length direction and are respectively connected to the source contacts and the drain contacts.

摘要翻译： MOS晶体管包括形成为栅格图案的栅极电极，由栅电极围绕的源极区域和漏极区域以及经由源极触点连接到源极区域的源极金属布线和经由漏极连接到漏极区域的漏极金属布线 联系人 源金属布线和漏极金属布线沿着栅电极的栅格的一个方向设置。 源极区域和漏极区域中的每一个是沿着每个金属布线的长度方向具有长边的矩形形状。 源极金属布线和漏极金属布线分别在长度方向上以锯齿形形式分别连接到源极触点和漏极触点。

公开(公告)号：US08507138B2

公开(公告)日：2013-08-13

申请号：US12456243

申请日：2009-06-12

申请人： Kouichi Yamada ,  Kazunori Fukuma ,  Makoto Wada

发明人： Kouichi Yamada ,  Kazunori Fukuma ,  Makoto Wada

IPC分类号： H01M8/04 ,  F04F5/48

CPC分类号： H01M8/04089 ,  F04F5/18 ,  F04F5/36 ,  F04F5/463 ,  Y10T137/2572

摘要： An ejector for a fuel cell system of the present invention includes a nozzle having a nozzle hole for discharging hydrogen supplied via an inlet port of an ejector body, a diffuser for mixing hydrogen discharged from the nozzle hole and hydrogen off-gas discharged and returned via a circulation passage from a fuel cell, a needle displacing in the axial direction by a driving force of a solenoid, and a bearing member held in a hollow portion of the nozzle, and having a through hole that movably supports the needle in the axial direction.

公开(公告)号：US20120142497A1

公开(公告)日：2012-06-07

申请号：US13311768

申请日：2011-12-06

申请人： Hiroshi ISHII ,  Sizuo Takatou ,  Kenichi Honda ,  Hajime Watanabe ,  Kouichi Yamada ,  Yasuyuki Murayama ,  Toshihiko Shiraishi ,  Shin Morishita

发明人： Hiroshi ISHII ,  Sizuo Takatou ,  Kenichi Honda ,  Hajime Watanabe ,  Kouichi Yamada ,  Yasuyuki Murayama ,  Toshihiko Shiraishi ,  Shin Morishita

IPC分类号： A63B24/00

CPC分类号： A63B24/0075 ,  A63B21/0056 ,  A63B21/0085 ,  A63B24/0087 ,  A63B2024/0093 ,  A63B2220/22 ,  A63B2220/51

摘要： A training system for training of part of a trainee's body includes a training machine, a control device controlling the training machine, and a display unit displaying a game screen. The training machine imposes a load on the trainee, with an MR-fluid load generating unit using MR fluid, which has viscosity varying with a magnetic field strength. The load is calculated on the basis of a target load and a relationship between the current in the MR-fluid load generating unit and the load generated by the MR-fluid load generating unit. The control device produces the game screen in correspondence with the trainee's training motion detected by a displacement detection sensor, and makes the display unit display the game screen, while controlling the load in the training machine.

摘要翻译： 用于训练学员身体的一部分的训练系统包括训练机，控制训练机的控制装置以及显示游戏画面的显示单元。 训练机对受训者施加负荷，使用MR流体负载产生单元，其使用具有随磁场强度变化的粘度的MR流体。 基于目标负荷和MR流体负荷产生单元中的电流与MR流体负载产生单元产生的负载之间的关系来计算负载。 控制装置根据由位移检测传感器检测到的受训者的训练动作产生游戏画面，并且在控制训练机器的负荷的同时使显示单元显示游戏画面。

公开(公告)号：US08050075B2

公开(公告)日：2011-11-01

申请号：US12266332

申请日：2008-11-06

申请人： Kouichi Yamada

发明人： Kouichi Yamada

IPC分类号： G11C17/00 ,  G11C8/00

CPC分类号： G11C17/06 ,  G11C5/025 ,  G11C7/1015 ,  G11C8/12 ,  G11C8/14

摘要： A memory is so formed that, in a first block and a second block each including a prescribed number of the bit lines arranged therein, positions of the bit lines simultaneously selected in the first and second blocks with reference to ends of the first and second blocks respectively are different from each other.

摘要翻译： 存储器被形成为使得在包括布置在其中的规定数量的位线的第一块和第二块中，参考第一和第二块的端部在第一和第二块中同时选择的位线的位置 分别是不同的。

公开(公告)号：US20110175449A1

公开(公告)日：2011-07-21

申请号：US13008414

申请日：2011-01-18

申请人： Shigeto KOBAYASHI ,  Kouichi Yamada ,  Yoshitaka Ueda ,  Atsushi Wada

发明人： Shigeto KOBAYASHI ,  Kouichi Yamada ,  Yoshitaka Ueda ,  Atsushi Wada

IPC分类号： H02J1/10

CPC分类号： H02J1/08 ,  G06F1/26 ,  H03K19/0175 ,  H03L5/00 ,  Y10T307/50

摘要： A power supply circuit generates the internal power supply voltage intVCC from a first power supply capable of supplying a first power supply voltage V1 and a second power supply capable of supplying a second power supply voltage V2, which is lower than the first power supply voltage V1. A first transistor TR1 is provided between the first power supply and an output node, whereas a second transistor TR2 is provided between the second power supply and the output node. A first supply unit supplies the inverted value of an output voltage of the first power supply or the inverted value of a voltage corresponding to the output voltage of the first power supply, to the gate input of the first transistor TR1. A second supply unit supplies the output voltage of the first power supply or the voltage corresponding to the output voltage of the first power supply, to the gate input of the second transistor TR2.

摘要翻译： 电源电路从能够提供第一电源电压V1的第一电源和能够提供低于第一电源电压V1的第二电源电压V2的第二电源产生内部电源电压intVCC 。 第一晶体管TR1设置在第一电源和输出节点之间，而第二晶体管TR2设置在第二电源和输出节点之间。 第一供电单元将第一电源的输出电压的反相值或与第一电源的输出电压对应的电压的反相值提供给第一晶体管TR1的栅极输入。 第二供应单元将第一电源的输出电压或与第一电源的输出电压相对应的电压提供给第二晶体管TR2的栅极输入。

公开(公告)号：US07704825B2

公开(公告)日：2010-04-27

申请号：US12149137

申请日：2008-04-28

申请人： Kouichi Yamada

发明人： Kouichi Yamada

IPC分类号： H01L21/8239 ,  H01L21/8246 ,  H01L21/8234 ,  H01L27/10 ,  H01L27/112 ,  H01L27/105

CPC分类号： H01L27/11253 ,  G11C11/15 ,  G11C17/06 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11213 ,  H01L27/11293 ,  H01L27/224 ,  Y10S257/903 ,  Y10S257/905 ,  Y10S257/909 ,  Y10S257/91

摘要： A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode.

摘要翻译： 提供了能够减小存储单元大小的存储器。 该存储器包括形成在半导体衬底的主表面的存储单元阵列区域上的第一导电型第一杂质区，用作用于存储单元中包含的二极管的第一电极和多个第二导电型第二杂质区， 以规定的间隔形成在第一杂质区域的表面上，各自用作二极管的第二电极。

公开(公告)号：US07593257B2

公开(公告)日：2009-09-22

申请号：US11353089

申请日：2006-02-14

申请人： Yoshiki Murayama ,  Kouichi Yamada

发明人： Yoshiki Murayama ,  Kouichi Yamada

IPC分类号： G11C11/34

CPC分类号： G11C11/22 ,  G11C13/0004 ,  G11C13/004

摘要： A memory capable of suppressing reduction of data determination accuracy is provided. This memory includes a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current, corresponding to the data of the memory cell, appearing on the bit line with the bipolar transistor.

摘要翻译： 提供了能够抑制数据判定精度降低的存储器。 该存储器包括连接到用于保持数据的位线的存储器单元和其基极连接到位线的双极晶体管。 在数据读取中，存储器通过放大与双极晶体管在位线上出现的存储单元的数据相对应的电流来读取数据。

公开(公告)号：US07366004B2

公开(公告)日：2008-04-29

申请号：US11328223

申请日：2006-01-10

申请人： Hideaki Miyamoto ,  Naofumi Sakai ,  Kouichi Yamada ,  Shigeharu Matsushita

发明人： Hideaki Miyamoto ,  Naofumi Sakai ,  Kouichi Yamada ,  Shigeharu Matsushita

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.

摘要翻译： 提供了能够抑制数据读取中的读取电压的降低而不管制造过程中的分散性的存储器。 该存储器包括电荷存储装置，第一场效应晶体管和数据确定装置。 存储器将第一场效应晶体管的控制端子和剩余的第一端子之间的电压设置为阈值电压，以使第一场效应晶体管处于ON和OFF之间的边界状态附近的截止状态 - 通过第一场效应晶体管的阈值电压。

公开(公告)号：US20060181945A1

公开(公告)日：2006-08-17

申请号：US11353089

申请日：2006-02-14

申请人： Yoshiki Murayama ,  Kouichi Yamada

发明人： Yoshiki Murayama ,  Kouichi Yamada

IPC分类号： G11C7/00

CPC分类号： G11C11/22 ,  G11C13/0004 ,  G11C13/004

摘要： A memory capable of suppressing reduction of data determination accuracy is provided. This memory comprises a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current, corresponding to the data of the memory cell, appearing on the bit line with the bipolar transistor.

摘要翻译： 提供了能够抑制数据判定精度降低的存储器。 该存储器包括连接到用于保持数据的位线的存储器单元和其基极连接到位线的双极晶体管。 在数据读取中，存储器通过放大与双极晶体管在位线上出现的存储单元的数据相对应的电流来读取数据。

公开(公告)号：US20060164877A1

公开(公告)日：2006-07-27

申请号：US11328223

申请日：2006-01-10

申请人： Hideaki Miyamoto ,  Naofumi Sakai ,  Kouichi Yamada ,  Shigeharu Matsushita

发明人： Hideaki Miyamoto ,  Naofumi Sakai ,  Kouichi Yamada ,  Shigeharu Matsushita

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.

摘要翻译： 提供了能够抑制数据读取中的读取电压的降低而不管制造过程中的分散性的存储器。 该存储器包括电荷存储装置，第一场效应晶体管和数据确定装置。 存储器将第一场效应晶体管的控制端子和剩余的第一端子之间的电压设置为阈值电压，以使第一场效应晶体管处于ON和OFF之间的边界状态附近的截止状态 - 通过第一场效应晶体管的阈值电压。