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    Data read/write control system and data read/write control method
    1.
    发明申请
    Data read/write control system and data read/write control method 审中-公开
    数据读/写控制系统和数据读写控制方式

    公开(公告)号：US20050066112A1

    公开(公告)日：2005-03-24

    申请号：US10942023

    申请日：2004-09-16

    Applicant: Takeshi Osakabe ,  Hiroyuki Kawaguchi ,  Yoshitaka Ueda ,  Shuji Takahashi

    Inventor： Takeshi Osakabe ,  Hiroyuki Kawaguchi ,  Yoshitaka Ueda ,  Shuji Takahashi

    IPC: G06F12/16 ,  G06F12/00 ,  G06F12/02 ,  G11C16/02

    CPC classification number: G06F12/0246

    Abstract: A data read/write control system includes memory divided into a plurality of blocks, a write unit, and a read unit. When writing data to one block of the plurality of blocks, the write unit compares a size of the data with a capacity of a blank area of the block. If the size of the data is larger, the write unit erases all data stored in the block and sequentially writes the data to the block from top or end. If, on the other hand, the size of the data is smaller, the write unit sequentially writes the data to the block from an area next to an area where data is stored. When reading data from the block, the read unit sequentially searches the block from top or end to find an area where data is written last, and reads the data stored in the area.

    Abstract translation: 数据读/写控制系统包括分成多个块的存储器，写单元和读单元。 当将数据写入多个块的一个块时，写入单元将数据的大小与块的空白区域的容量进行比较。 如果数据的大小较大，则写入单元擦除存储在块中的所有数据，并从顶部或末端顺序地将数据写入块。 另一方面，如果数据的大小较小，则写入单元从存储数据的区域旁边的区域顺序地将数据写入块中。 当从块读取数据时，读取单元从顶部或末端顺序地搜索块以找到最后写入数据的区域，并读取存储在该区域中的数据。

    Semiconductor integrated circuit related to a circuit operating on the basis of a clock signal
    2.
    发明授权
    Semiconductor integrated circuit related to a circuit operating on the basis of a clock signal 有权
    与基于时钟信号工作的电路有关的半导体集成电路

    公开(公告)号：US06707328B2

    公开(公告)日：2004-03-16

    申请号：US09745990

    申请日：2000-12-26

    Applicant: Yoshitaka Ueda ,  Isao Ogura

    Inventor： Yoshitaka Ueda ,  Isao Ogura

    IPC: H03L700

    CPC classification number: H03K3/013 ,  H01L27/0207 ,  H01L27/11807 ,  H03K3/0372 ,  H03K19/00361

    Abstract: A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input terminal to each logic circuit, a second power supply wire for supplying the high-potential side power supply voltage from a second input terminal to each logic circuit and a third power supply wire for supplying the high-potential side power supply voltage from a third input terminal to each logic circuit. The logic circuit (DFF circuit) includes two stages of latch circuits and a clock signal inversion circuit. Only the clock signal inversion circuit is connected with the first power supply wire, while the second power supply wire is connected with the remaining latch circuits.

    Abstract translation: 一种半导体集成电路，其中包括同步设计为与时钟信号同步操作的多个逻辑电路，用于从第一输入端子向每个逻辑电路提供高电位侧电源电压的第一电源线，第二电源 用于从第二输入端子向每个逻辑电路提供高电位侧电源电压的电源线和用于将高电位侧电源电压从第三输入端子提供给每个逻辑电路的第三电源线。 逻辑电路（DFF电路）包括两级锁存电路和时钟信号反相电路。 只有时钟信号反相电路与第一电源线连接，而第二电源线与剩余的锁存电路连接。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08513716B2

    公开(公告)日：2013-08-20

    申请号：US13016481

    申请日：2011-01-28

    Applicant: Yoshitaka Ueda ,  Kouichi Yamada ,  Atsushi Wada ,  Shigeto Kobayashi

    Inventor： Yoshitaka Ueda ,  Kouichi Yamada ,  Atsushi Wada ,  Shigeto Kobayashi

    IPC: H01L29/78

    CPC classification number: H01L27/105

    Abstract: A MOS transistor includes a gate electrode formed in a grid pattern, source regions and drain regions each surrounded by the gate electrode, and a source metal wiring connected to the source regions via source contacts and a drain metal wiring connected to the drain regions via drain contacts. The source metal wiring and the drain metal wiring are disposed along one direction of the grid of the gate electrode. Each of the source regions and the drain regions is a rectangular form having its long side along the length direction of each metal wiring. The source metal wiring and the drain metal wiring are each formed in a zigzag manner in the length direction and are respectively connected to the source contacts and the drain contacts.

    Abstract translation: MOS晶体管包括形成为栅格图案的栅极电极，由栅电极围绕的源极区域和漏极区域以及经由源极触点连接到源极区域的源极金属布线和经由漏极连接到漏极区域的漏极金属布线 联系人 源金属布线和漏极金属布线沿着栅电极的栅格的一个方向设置。 源极区域和漏极区域中的每一个是沿着每个金属布线的长度方向具有长边的矩形形状。 源极金属布线和漏极金属布线分别在长度方向上以锯齿形形式分别连接到源极触点和漏极触点。

    POWER SUPPLY CIRCUIT
    6.
    发明申请
    POWER SUPPLY CIRCUIT 有权
    电源电路

    公开(公告)号：US20110175449A1

    公开(公告)日：2011-07-21

    申请号：US13008414

    申请日：2011-01-18

    Applicant: Shigeto KOBAYASHI ,  Kouichi Yamada ,  Yoshitaka Ueda ,  Atsushi Wada

    Inventor： Shigeto KOBAYASHI ,  Kouichi Yamada ,  Yoshitaka Ueda ,  Atsushi Wada

    IPC: H02J1/10

    CPC classification number: H02J1/08 ,  G06F1/26 ,  H03K19/0175 ,  H03L5/00 ,  Y10T307/50

    Abstract: A power supply circuit generates the internal power supply voltage intVCC from a first power supply capable of supplying a first power supply voltage V1 and a second power supply capable of supplying a second power supply voltage V2, which is lower than the first power supply voltage V1. A first transistor TR1 is provided between the first power supply and an output node, whereas a second transistor TR2 is provided between the second power supply and the output node. A first supply unit supplies the inverted value of an output voltage of the first power supply or the inverted value of a voltage corresponding to the output voltage of the first power supply, to the gate input of the first transistor TR1. A second supply unit supplies the output voltage of the first power supply or the voltage corresponding to the output voltage of the first power supply, to the gate input of the second transistor TR2.

    Abstract translation: 电源电路从能够提供第一电源电压V1的第一电源和能够提供低于第一电源电压V1的第二电源电压V2的第二电源产生内部电源电压intVCC 。 第一晶体管TR1设置在第一电源和输出节点之间，而第二晶体管TR2设置在第二电源和输出节点之间。 第一供电单元将第一电源的输出电压的反相值或与第一电源的输出电压对应的电压的反相值提供给第一晶体管TR1的栅极输入。 第二供应单元将第一电源的输出电压或与第一电源的输出电压相对应的电压提供给第二晶体管TR2的栅极输入。

    Semiconductor integrated circuit with flip-flop circuits mounted thereon
    7.
    发明授权
    Semiconductor integrated circuit with flip-flop circuits mounted thereon 有权
    具有安装在其上的触发器电路的半导体集成电路

    公开(公告)号：US07746138B2

    公开(公告)日：2010-06-29

    申请号：US12044406

    申请日：2008-03-07

    Applicant: Satoru Sekine ,  Yoshitaka Ueda ,  Takashi Asano ,  Shinji Furuichi ,  Atsushi Wada

    Inventor： Satoru Sekine ,  Yoshitaka Ueda ,  Takashi Asano ,  Shinji Furuichi ,  Atsushi Wada

    IPC: H03K3/00

    CPC classification number: H03K3/35625

    Abstract: A plurality of flip-flop circuits, having different circuit configurations, which perform an identical digital signal processing are mixed on a single semiconductor substrate. A first flip-flop circuit among the plurality of flip-flop circuits receives a clock signal supplied from outside the flip-flop circuits, through at least two stage inverters, and operates with clock signals outputted from the inverters. A second flip-flop circuit receives the clock signal supplied from outside the flip-flop circuits through at least one inverter having a less number of stages than the number of stages of the inverter contained in the first flip-flop circuit, and operates with at least one of the clock signal and a clock signal outputted from the inverter.

    Abstract translation: 具有不同电路结构的执行相同数字信号处理的多个触发电路混合在单个半导体衬底上。 多个触发器电路中的第一触发器电路通过至少两级反相器接收从触发器电路外部提供的时钟信号，并且利用从反相器输出的时钟信号进行操作。 第二触发器电路通过至少一个具有比包含在第一触发器电路中的反相器的级数少的级数的反相器接收从触发器电路的外部提供的时钟信号，并且以 至少一个时钟信号和从逆变器输出的时钟信号。

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