公开(公告)号：US20190296020A1

公开(公告)日：2019-09-26

申请号：US16412447

申请日：2019-05-15

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/764 ,  H01L29/06 ,  H01L29/49

Abstract: A semiconductor structure includes a semiconductor substrate having a trench isolation region formed therein. A conductive gate electrode is buried in the trench isolation region. An air gap is disposed between the conductive gate electrode and the semiconductor substrate.

公开(公告)号：US20190296019A1

公开(公告)日：2019-09-26

申请号：US15961827

申请日：2018-04-24

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Po-Han Wu ,  Li-Wei Feng ,  Shih-Han Hung ,  Fu-Che Lee ,  Chien-Cheng Tsai

IPC: H01L27/108 ,  H01L21/768

Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.

公开(公告)号：US10361080B2

公开(公告)日：2019-07-23

申请号：US15641235

申请日：2017-07-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L21/3105 ,  H01L21/311 ,  H01L21/033 ,  H01L27/108 ,  H01L21/3213

Abstract: A patterning method is disclosed. A hard mask layer, a lower pattern transfer layer, an upper pattern transfer layer are formed on a target layer. A first SARP process is performed to pattern the upper pattern transfer layer into an upper pattern mask. A second SARP process is performed to pattern the lower pattern transfer layer into a lower pattern mask. The upper pattern mask and the lower pattern mask define hole patterns. The hole patterns is filled with a dielectric layer. The dielectric layer and the upper pattern mask are etched back until the lower pattern mask is exposed. The lower pattern mask is removed, thereby forming island patterns. Using the island patterns as an etching hard mask, the hard mask layer is patterned into hard mask patterns. Using the hard mask patterns as an etching hard mask, the target layer is patterned into target patterns.

公开(公告)号：US20190172831A1

公开(公告)日：2019-06-06

申请号：US15857642

申请日：2017-12-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Yu-Cheng Tung ,  Fu-Che Lee

IPC: H01L27/108

Abstract: A layout of semiconductor structure includes plural patterns arranged along a first direction to form plural columns, with each pattern spaced from each other. A region is defined by the patterns, and which includes a first edge and a second edge, with the first edge extended along the first direction, and the second edge extended along a second direction different from the first direction and being serrated. The second edge includes plural fragments, with each fragment being defined by at least two patterns. The present invention also provided a semiconductor device and a method of forming the same.

公开(公告)号：US20190172722A1

公开(公告)日：2019-06-06

申请号：US16158316

申请日：2018-10-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Wei-Hsin Liu ,  Ying-Chih Lin ,  Jui-Min Lee ,  Gang-Yi Lin ,  Fu-Che Lee

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/033 ,  H01L27/105

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/1052

Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a target layer is provided, and a mask structure is formed on the target layer, with the mask structure including a first mask layer a sacrificial layer and a second mask layer. The first mask layer and the second mask layer include the same material but in different containing ratio. Next, the second mask layer and the sacrificial layer are patterned, to form a plurality of mandrels. Then, a plurality of spacer patterns are formed to surround the mandrels, and then transferred into the first mask layer to form a plurality of opening not penetrating the first mask layer. Finally, the first mask layer is used as a mask to etch the target layer, to form a plurality of target patterns.

公开(公告)号：US10312090B2

公开(公告)日：2019-06-04

申请号：US16003058

申请日：2018-06-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L21/311 ,  H01L21/033 ,  H01L27/108

Abstract: A patterning method is disclosed. A substrate having a hard mask layer and a first material layer formed thereon is provided. The first material layer is patterned into first array patterns and first peripheral patterns. The first array patterns are further transferred into first spacer patterns. Subsequently, a planarization layer and a second material layer are successively formed on the substrate. The second material layer is patterned into second array patterns and second peripheral patterns. The second array patterns are further transferred into second spacer patterns. The second spacer patterns partially overlap the first spacer patterns. The second peripheral patterns do not overlap the first peripheral pattern. The first spacer patterns not overlapped by the second spacer patterns are removed to obtain third array patterns. The hard mask layer is then etched using the third array patterns, the second peripheral patterns and the first peripheral patterns as an etching mask.

公开(公告)号：US20190123135A1

公开(公告)日：2019-04-25

申请号：US16129782

申请日：2018-09-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L49/02 ,  H01L27/108

Abstract: The present invention discloses a method of manufacturing a capacitor, which includes the steps of forming a capacitor recess in a sacrificial layer, wherein the sidewall of capacitor recess has a wave profile, forming a bottom electrode layer on the sidewall of capacitor recess, filling up the capacitor recess with a supporting layer, removing the sacrificial layer to forma capacitor pillar made up by the bottom electrode layer and the supporting layer, forming a capacitor dielectric layer on the capacitor pillar, and forming a top electrode layer on the capacitor dielectric layer.

公开(公告)号：US10217750B1

公开(公告)日：2019-02-26

申请号：US15712133

申请日：2017-09-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Kuan-Chun Lin ,  Chi-Mao Hsu ,  Shu-Yen Chan ,  Shih-Fang Tzou ,  Tsuo-Wen Lu ,  Tien-Chen Chan ,  Feng-Yi Chang ,  Shih-Kuei Yen ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/28

Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

公开(公告)号：US20190051654A1

公开(公告)日：2019-02-14

申请号：US16011652

申请日：2018-06-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L27/108

Abstract: A method of manufacturing contacts is provided in the present invention, which include the steps of forming a plurality of mask bars on a substrate, forming a circular mask surrounding each mask bar, wherein the circular masks connect each other and define a plurality of opening patterns collectively with the mask bars, using the mask bars and the circular masks as etch masks to perform an etch process and to transfer the opening patterns and form a plurality recesses in the substrate, and filling up the recesses with metal to form contacts.

公开(公告)号：US10204911B2

公开(公告)日：2019-02-12

申请号：US15859763

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L21/033 ,  H01L21/311 ,  H01L27/108 ,  H01L21/02 ,  H01L49/02 ,  H01L21/027

Abstract: A method for fabricating a capacitor includes providing a substrate and a first etching stop layer on the substrate; forming a plurality of first spacers on the first etching stop layer; forming an organic layer and a second etching stop layer sequentially on the first spacers, the organic layer covering the first spacers; forming a plurality of second spacers on the second etching stop layer, each second spacer crossing the first spacers; transferring a pattern of the second spacers to the organic layer to form an organic pattern; performing an etching process using the organic pattern and the first spacers as a mask to form an etching stop pattern and remove the second etching stop layer; transferring the etching stop pattern to the substrate to form a plurality of through holes.