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147 条记录 (耗时 0.023 秒)

    Supply noise reduction in memory device column selection
    82.
    发明授权
    Supply noise reduction in memory device column selection 有权

    公开(公告)号：US06584035B2

    公开(公告)日：2003-06-24

    申请号：US10032375

    申请日：2001-12-21

    申请人： Ercole Di lorio ,  Giulio G. Marotta ,  Giovanni Santin ,  Tommaso Vali

    发明人： Ercole Di lorio ,  Giulio G. Marotta ,  Giovanni Santin ,  Tommaso Vali

    IPC分类号： G11C800

    CPC分类号： G11C16/08 ,  G11C7/1048 ,  G11C8/10 ,  G11C2207/002

    摘要： Column select circuits having improved immunity to supply potential noise during sensing of the programmed state of a target memory cell are suited for use in low-voltage memory devices. Such column select circuits contain driver circuits having a filtered path and an unfiltered path for applying a supply potential to a gate of a pass transistor. The unfiltered path is utilized during a first sensing phase, such as during decoding or precharging of the bit lines, when transition speed of the pass transistors is desired. The filtered path is utilized at least during a second sensing phase while the sensing device is detecting the programmed state of the target memory cell. By reducing the noise of the supply potential using the filtered path, margins are improved on the sensing device and the sensing device is thus capable of operating at lower supply potentials.

    SELECTIVE SLOW PROGRAMMING CONVERGENCE IN A FLASH MEMORY DEVICE
    84.
    发明申请
    SELECTIVE SLOW PROGRAMMING CONVERGENCE IN A FLASH MEMORY DEVICE 审中-公开
    闪存存储器中的选择性慢速编程融合

    公开(公告)号：US20080094912A1

    公开(公告)日：2008-04-24

    申请号：US11958620

    申请日：2007-12-18

    申请人： Michele Incarnati ,  Giovanni Santin ,  Tommaso Vali

    发明人： Michele Incarnati ,  Giovanni Santin ,  Tommaso Vali

    IPC分类号： G11C16/06

    CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3404 ,  G11C2211/5621

    摘要： A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to that particular cell is biased with an intermediate voltage that slows down the change in the Vt of the cell. The other cells continue to be programmed at their normal pace. As the Vt for each cell reaches the pre-verify level, it is biased with the intermediate voltage. All of the bit lines are biased with an inhibit voltage as their threshold voltages reach the verify voltage threshold.

    摘要翻译： 多个存储器单元被编程，其中增加的编程脉冲被施加到存储器单元耦合到的字线。 在每个脉冲之后，验证操作确定每个单元的阈值电压。 当阈值电压达到预验证阈值时，只有连接到该特定单元的位线被中间电压偏置，该中间电压降低了单元的Vcc变化。 其他细胞继续按其正常速度进行编程。 由于每个单元的V OUT达到预验证电平，所以它被中间电压偏置。 当它们的阈值电压达到验证电压阈值时，所有位线都被抑制电压偏置。

    Single latch data circuit in a multiple level call non-volatile memory device
    86.
    发明授权
    Single latch data circuit in a multiple level call non-volatile memory device 有权
    单级锁存数据电路在多级单元非易失性存储器件中

    公开(公告)号：US07630241B2

    公开(公告)日：2009-12-08

    申请号：US12170563

    申请日：2008-07-10

    申请人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

    发明人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

    IPC分类号： G11C11/34

    CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/28 ,  G11C2211/5642 ,  G11C2211/5647

    摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.

    摘要翻译： 单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。 该电路由具有反向节点和非反相节点的锁存器组成。 第一控制晶体管选择性地将非反相节点耦合到锁存器输出。 第二控制晶体管选择性地将反相节点耦合到锁存器输出。 复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

    Single latch data circuit in a multiple level cell non-volatile memory device
    89.
    发明授权
    Single latch data circuit in a multiple level cell non-volatile memory device 有权
    单级锁存数据电路在多级单元非易失性存储器件中

    公开(公告)号：US07417894B2

    公开(公告)日：2008-08-26

    申请号：US11506428

    申请日：2006-08-18

    申请人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

    发明人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

    IPC分类号： G11C11/34

    CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/28 ,  G11C2211/5642 ,  G11C2211/5647

    摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.

    摘要翻译： 单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。 该电路由具有反向节点和非反相节点的锁存器组成。 第一控制晶体管选择性地将非反相节点耦合到锁存器输出。 第二控制晶体管选择性地将反相节点耦合到锁存器输出。 复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

    Selective slow programming convergence in a flash memory device
    90.
    发明授权
    Selective slow programming convergence in a flash memory device 有权
    闪存设备中选择性慢的编程收敛

    公开(公告)号：US07324383B2

    公开(公告)日：2008-01-29

    申请号：US11414982

    申请日：2006-05-01

    申请人： Michele Incarnati ,  Giovanni Santin ,  Tommaso Vali

    发明人： Michele Incarnati ,  Giovanni Santin ,  Tommaso Vali

    IPC分类号： G11C16/06

    CPC分类号： G11C16/3404

    摘要： A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to that particular cell is biased with an intermediate voltage that slows down the change in the Vt of the cell. The other cells continue to be programmed at their normal pace. As the Vt for each cell reaches the pre-verify level, it is biased with the intermediate voltage. All of the bit lines are biased with an inhibit voltage as their threshold voltages reach the verify voltage threshold.

    摘要翻译： 多个存储器单元被编程，其中增加的编程脉冲被施加到存储器单元耦合到的字线。 在每个脉冲之后，验证操作确定每个单元的阈值电压。 当阈值电压达到预验证阈值时，只有连接到该特定单元的位线被中间电压偏置，该中间电压降低了单元的Vcc变化。 其他细胞继续按其正常速度进行编程。 由于每个单元的V OUT达到预验证电平，所以它被中间电压偏置。 当它们的阈值电压达到验证电压阈值时，所有位线都被抑制电压偏置。