公开(公告)号：US20050060682A1

公开(公告)日：2005-03-17

申请号：US10981343

申请日：2004-11-03

Applicant: Shao-Po Wu ,  Seonghun Cho ,  Yao-Ting Wang

Inventor： Shao-Po Wu ,  Seonghun Cho ,  Yao-Ting Wang

IPC: G03F1/00 ,  G06F17/50 ,  G03F9/00 ,  G06F19/00 ,  G21K5/00

CPC classification number: G03F1/30

Abstract: A method of assigning phases to shifters on a layout is provided. The method includes creating a link between any two shifters within a predetermined distance from each other. In one embodiment, the predetermined distance is larger than a minimum feature size on the layout, and smaller than a combined minimum pitch and regulator width. A weight can be assigned to each created link. Phases can be assigned to the shifters, wherein if a phase-shift conflict exists on the layout, then one or more links can be broken based on their weight.

Abstract translation: 提供了一种在布局上为移位器分配相位的方法。 该方法包括在彼此之间的预定距离内创建任何两个移位器之间的链接。 在一个实施例中，预定距离大于布局上的最小特征尺寸，并且小于组合的最小间距和调节器宽度。 可以将权重分配给每个创建的链接。 可以将相位分配给移位器，其中如果在布局上存在相移冲突，则可以基于它们的权重来断开一个或多个链路。

公开(公告)号：US06818385B2

公开(公告)日：2004-11-16

申请号：US10341290

申请日：2003-01-13

Applicant: Yao-Ting Wang ,  Yagyensh C. Pati

Inventor： Yao-Ting Wang ,  Yagyensh C. Pati

IPC: G03F900

CPC classification number: G03F7/70283 ,  G03F1/26 ,  G03F1/30 ,  G03F1/34 ,  G03F1/36 ,  G03F1/70 ,  G03F7/2022 ,  G03F7/70433 ,  G03F7/70441 ,  G03F7/705 ,  G06F17/5068

Abstract: A method for manufacturing integrated circuits using opaque field, phase shift masking. One embodiment of the invention includes using a two mask process. The first mask is an opaque-field phase shift mask and the second mask is a single phase structure mask. A phase shift window is aligned with the opaque field using a phase shift overlap area on the opaque field. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask.

Abstract translation: 一种使用不透光场，相移屏蔽制造集成电路的方法。 本发明的一个实施例包括使用两个掩模过程。 第一掩模是不透明场相移掩模，第二掩模是单相结构掩模。 使用不透明场上的相移重叠区域将相移窗与不透明场对准。 相移掩模主要限定需要相移的区域。 单相结构掩模主要限定不需要相移的区域。 单相结构掩模还防止相移区域的擦除，并且防止产生否则将由相移掩模产生的不期望的伪影区域。

公开(公告)号：US06453452B1

公开(公告)日：2002-09-17

申请号：US09154397

申请日：1998-09-16

Applicant: Fang-Cheng Chang ,  Yao-Ting Wang ,  Yagyensh C. Pati

Inventor： Fang-Cheng Chang ,  Yao-Ting Wang ,  Yagyensh C. Pati

IPC: G06F1750

CPC classification number: G06F17/5068

Abstract: A method and apparatus for performing an operation on hierarchically described integrated circuit layouts such that the original hierarchy of the layout is maintained is provided. The method comprises providing a hierarchically described layout as a first input and providing a particular set of operating criteria corresponding to the operation to be performed as a second input. The mask operation, which may include operations such as OPC and logical operations such as NOT and OR, is then performed on the layout in accordance with the particular set of operating criteria. A first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout is then generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated. As the first program data is maintained in a true hierarchical format, layouts which are operated upon in accordance with this method are able to be processed through conventional design rule checkers. Further, this method is capable of being applied to all types of layouts including light and dark field designs and phase shifting layouts.

Abstract translation: 一种用于对分级描述的集成电路布局执行操作的方法和装置，从而提供维护布局的原始层级。 该方法包括提供分层描述的布局作为第一输入，并提供与作为第二输入执行的操作相对应的特定操作标准集合。 然后可以根据特定的操作标准集在布局上执行掩模操作，其可以包括诸如OPC和诸如NOT和OR的逻辑操作的操作。 然后响应于布局操作​​产生包括对应于分层描述的布局的分层配置的校正数据的第一程序数据，使得如果第一程序数据被应用于平坦化布局，则输出包括表示执行操作的结果的数据 将生成布局。 由于第一程序数据以真正的分层格式维护，所以根据该方法操作的布局能够通过常规的设计规则检查器进行处理。 此外，该方法能够应用于所有类型的布局，包括浅色和暗场设计以及相移布局。

公开(公告)号：US06370679B1

公开(公告)日：2002-04-09

申请号：US09154415

申请日：1998-09-16

Applicant: Fang-Cheng Chang ,  Yao-Ting Wang ,  Yagyensh C. Pati

Inventor： Fang-Cheng Chang ,  Yao-Ting Wang ,  Yagyensh C. Pati

IPC: G06F760

CPC classification number: G03F1/36

Abstract: A method and apparatus for the correction of integrated circuit layouts for optical proximity effects which maintains the original true hierarchy of the original layout is provided. Also provided is a method and apparatus for the design rule checking of layouts which have been corrected for optical proximity effects. The OPC correction method comprises providing a hierarchically described integrated circuit layout as a first input, and a particular set of OPC correction criteria as a second input. The integrated circuit layout is then analyzed to identify features of the layout which meet the provided OPC correction criteria. After the areas on the mask which need correction have been identified, optical proximity correction data is generated in response to the particular set of correction criteria. Finally, a first program data is generated which stores the generated optical proximity correction data in a hierarchical structure that corresponds to the hierarchical structure of the integrated circuit layout. As the output correction data is maintained in true hierarchical format, layouts which are OPC corrected according to this method are able to be processed through conventional design rule checkers with no altering of the data.

Abstract translation: 提供了用于校正维持原始布局的原始真实层级的光学邻近效应的集成电路布局的方法和装置。 还提供了用于对光学邻近效应进行了校正的布局的设计规则检查的方法和装置。 OPC校正方法包括提供分级描述的集成电路布局作为第一输入和作为第二输入的特定的OPC校正标准集合。 然后分析集成电路布局以识别满足所提供的OPC校正标准的布局的特征。 在已经识别出需要校正的掩模上的区域之后，响应于特定的校正标准集而产生光学邻近校正数据。 最后，生成将生成的光学邻近校正数据存储在与集成电路布局的层次结构对应的层次结构中的第一程序数据。 由于输出校正数据以真实的分层格式保持，所以根据该方法校正OPC的布局能够通过传统的设计规则检查器进行处理，而不改变数据。

公开(公告)号：US5858580A

公开(公告)日：1999-01-12

申请号：US931921

申请日：1997-09-17

Applicant: Yao-Ting Wang ,  Yagyensh C. Pati

Inventor： Yao-Ting Wang ,  Yagyensh C. Pati

IPC: G03F1/00 ,  G03F1/26 ,  G03F1/30 ,  G03F1/36 ,  G03F7/20 ,  G06F17/50 ,  G03F9/00

CPC classification number: G03F1/30 ,  G03F1/26 ,  G03F1/36 ,  G03F1/70 ,  G03F7/2022 ,  G03F7/70283 ,  G03F7/70433 ,  G03F7/70441 ,  G03F7/705 ,  G06F17/5068

Abstract: A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.