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公开(公告)号：US07216320B2
公开(公告)日：2007-05-08
申请号：US10984443
申请日：2004-11-08
申请人： Li-Fu Chang , Yao-Ting Wang , Fang-Cheng Chang
发明人： Li-Fu Chang , Yao-Ting Wang , Fang-Cheng Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.
摘要翻译： 提供了集成电路（“IC”）制造中定时驱动形状闭合的系统和方法。 这些集成设计制造过程（“IDMP”）包括将IC制造定时和几何验证过程的信息集成到IC设计中的增量流。 增量流是增量流，其包括用于处理与电路表征参数相关联的差异信息的δ-几何时序预测过程和/或Δ-时间形状预测过程。 delta流程使用与电路特性参数对应的差异或增量信息独立地重新表征IC设计。 增量流提供增量或重新表征器件和互连结构的相应参数的增量输出（增量），而不需要生成新的电路特征参数，而无需重新处理IC设计的所有信息。
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公开(公告)号：US20060242618A1
公开(公告)日：2006-10-26
申请号：US11354398
申请日：2006-02-14
申请人： Yao-Ting Wang , Chi-Ming Tsai , Fang-Cheng Chang
发明人： Yao-Ting Wang , Chi-Ming Tsai , Fang-Cheng Chang
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36 , G03F7/705 , G06F17/5081
摘要： Systems and methods are provided for programming and running simulation engines of lithographic simulations on GPUs. This integration of lithographic simulations includes the hosting on one or more GPUs of any of a variety of lithographic techniques, including for example resolution enhancement technologies, optical proximity correction, optical rule-checking or lithography checking, and model-based DRC, where operations of one or more techniques are run in parallel. The systems and methods provided also include the integration of lithographic geometry operations into GPUs to obtain improved performance. Examples of this integration include a Design Rule Checker (DRC), parasitic extraction, and placement and route for example.
摘要翻译： 提供了用于编程和运行GPU上光刻仿真的仿真引擎的系统和方法。 光刻模拟的这种集成包括在一个或多个GPU上托管各种光刻技术中的任何一种，包括例如分辨率增强技术，光学邻近校正，光学规则检查或光刻检查以及基于模型的DRC，其中操作 一个或多个技术并行运行。 所提供的系统和方法还包括将平版印刷几何操作集成到GPU中以获得改进的性能。 这种集成的示例包括设计规则检查器（DRC），寄生提取，以及放置和路由。
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公开(公告)号：US07052826B2
公开(公告)日：2006-05-30
申请号：US10918483
申请日：2004-08-16
申请人： Ching Chin Lai , Fang Cheng Chang , Ming En Chen , Jung Hsiang Chu , Kuang Ling Hsaio , Yun Lin Jang
发明人： Ching Chin Lai , Fang Cheng Chang , Ming En Chen , Jung Hsiang Chu , Kuang Ling Hsaio , Yun Lin Jang
IPC分类号： G03C1/492
CPC分类号： G03F7/00
摘要： A monitoring method for photoresist regeneration, a process and a system for the same are provided. In the photoresist regeneration process of the invention, the solid content and viscosity of photoresist are adjusted by condensation under reduced pressure or dilution with photoresist thinner until the final solid content and viscosity reach the predetermined values thereof obtained through the quantification equation of the invention and then the waste photoresist is caused to pass through filters for removing pollution particles contained therein, such that the regenerated photoresist is acquired.
摘要翻译： 提供了一种用于光致抗蚀剂再生的监测方法，其工艺和系统。 在本发明的光致抗蚀剂再生方法中，光致抗蚀剂的固体含量和粘度通过在减压下缩合或用光致抗蚀剂稀释剂进行稀释来调节，直到最终固体含量和粘度达到通过本发明的定量方程获得的预定值，然后 使废光致抗蚀剂通过用于除去其中所含的污染颗粒的过滤器，从而获得再生的光致抗蚀剂。
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公开(公告)号：US07014955B2
公开(公告)日：2006-03-21
申请号：US09941453
申请日：2001-08-28
摘要： Automated techniques for identifying dummy/main features on a mask layer are provided. In a multiple mask layer technique, the definition of a dummy/main feature can be based on connectivity information or functional association information. In a geometry technique, the definition of a dummy/main feature can be based on a feature size, a feature shape, a pattern of features, or a proximity of a feature to a neighboring feature. In one embodiment, multiple definitions and multiple techniques can be used.
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公开(公告)号：US20050244761A1
公开(公告)日：2005-11-03
申请号：US10918483
申请日：2004-08-16
申请人： Ching-Chin Lai , Fang-Cheng Chang , Ming-En Chen , Jung-Hsiang Chu , Kuang-Ling Hsiao , Yun-Lin Jang
发明人： Ching-Chin Lai , Fang-Cheng Chang , Ming-En Chen , Jung-Hsiang Chu , Kuang-Ling Hsiao , Yun-Lin Jang
CPC分类号： G03F7/00
摘要： A monitoring method for photoresist regeneration, a process and a system for the same are provided. In the photoresist regeneration process of the invention, the solid content and viscosity of photoresist are adjusted by condensation under reduced pressure or dilution with photoresist thinner until the final solid content and viscosity reach the predetermined values thereof obtained through the quantification equation of the invention and then the waste photoresist is caused to pass through filters for removing pollution particles contained therein, such that the regenerated photoresist is acquired.
摘要翻译： 提供了一种用于光致抗蚀剂再生的监测方法，其工艺和系统。 在本发明的光致抗蚀剂再生方法中，光致抗蚀剂的固体含量和粘度通过在减压下缩合或用光致抗蚀剂稀释剂进行稀释来调节，直到最终固体含量和粘度达到通过本发明的定量方程获得的预定值，然后 使废光致抗蚀剂通过用于除去其中所含的污染颗粒的过滤器，从而获得再生的光致抗蚀剂。
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6.发明授权Method and apparatus for exposing a wafer using multiple masks during an integrated circuit manufacturing process 有权在集成电路制造过程中使用多个掩模曝光晶片的方法和装置公开(公告)号：US06795168B2
公开(公告)日：2004-09-21
申请号：US10117838
申请日：2002-04-08
IPC分类号： G03B2754
CPC分类号： G03F7/70208 , G03F7/70283
摘要： One embodiment of the invention provides a system that facilitates exposing a wafer through at least two masks during an integrated circuit manufacturing process. The system includes a radiation source and two or more illuminators. Each of these illuminators receives radiation from the radiation source, and uses the radiation to illuminate a reticle holder. The radiation that passes through each reticle holder is then combined in an optical combiner, before passing through an imaging optics, which projects the combined radiation onto a semiconductor wafer.
摘要翻译： 本发明的一个实施例提供一种在集成电路制造过程中有助于使晶片通过至少两个掩模的系统。 该系统包括辐射源和两个或更多个照明器。 这些照明器中的每一个接收来自辐射源的辐射，并且使用辐射来照射标线架座。 然后通过每个光罩保持器的辐射在光合成器中通过成像光学器件，成像光学器件将组合的辐射投影到半导体晶片上。
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公开(公告)号：US06757645B2
公开(公告)日：2004-06-29
申请号：US09130996
申请日：1998-08-07
IPC分类号： G06F1750
CPC分类号： G06T7/0004 , G03F1/26 , G03F1/36 , G03F1/84 , G03F7/70441 , G03F7/705 , G06F17/5068 , G06T2207/30148
摘要： A method and apparatus for inspecting a photolithography mask for defects is provided. The inspection method comprises providing a defect area image to an image simulator wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography parameters as a second input to the image simulator. The defect area image may be provided by an inspection tool which scans the photolithography mask for defects using a high resolution microscope and captures images of areas of the mask around identified potential defects. The image simulator generates a first simulated image in response to the defect area image and the set of lithography parameters. The first simulated image is a simulation of an image which would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask. The method may also include providing a second simulated image which is a simulation of the wafer print of the portion of the design mask which corresponds to the portion represented by the defect area image. The method also provides for the comparison of the first and second simulated images in order to determine the printability of any identified potential defects on the photolithography mask. A method of determining the process window effect of any identified potential defects is also provided for.
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公开(公告)号：US06584609B1
公开(公告)日：2003-06-24
申请号：US09514551
申请日：2000-02-28
IPC分类号： G06F1750
CPC分类号： G03F1/70 , G03F1/36 , G06F17/5068
摘要： A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.
摘要翻译： 公开了一种半导体布局测试和校正系统。 该系统结合基于规则的光学邻近校正和基于模型的光学邻近校正，以便测试和校正半导体布局。 在第一实施例中，半导体布局首先由基于规则的光学邻近校正系统处理，然后由基于模型的光学邻近校正系统进行处理。 在另一个实施例中，系统首先使用基于规则的光学邻近校正系统处理半导体布局，然后使用基于模型的光学邻近校正系统来选择性地处理困难的特征。 在另一个实施例中，系统使用基于规则的光学邻近校正系统或基于模型的光学邻近校正系统选择性地处理半导体布局的各种特征。
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9.发明授权General purpose shape-based layout processing scheme for IC layout modifications 有权用于IC布局修改的通用形状布局处理方案公开(公告)号：US06523162B1
公开(公告)日：2003-02-18
申请号：US09632080
申请日：2000-08-02
IPC分类号： G06F1750
CPC分类号： G03F1/36 , G06F17/5081
摘要： Layout processing can be applied to an integrated circuit (IC) layout using a shape-based system. A shape can be defined by a set of associated edges in a specified configuration. A catalog of shapes is defined and layout processing actions are associated with the various shapes. Each layout processing action applies a specified layout modification to its associated shape. A shape-based rule system advantageously enables efficient formulation and precise application of layout modifications. Shapes/actions can be provided as defaults, can be retrieved from a remote source, or can be defined by the user. The layout processing actions can be compiled in a bias table. The bias table can include both rule-based and model-based actions, and can also include single-edge shapes for completeness. The scanning of the IC layout can be performed in order of increasing or decreasing complexity, or can be specified by the user. The appropriate layout processing actions are applied to matching portions of the IC layout to form the corrected photomask layout. This process can be sequential or batch mode. Shape and action conflicts can be resolved by marking identified/modified elements or by designing rules for orderly resolution of any inconsistencies or overlaps.
摘要翻译： 布局处理可以应用于使用基于形状的系统的集成电路（IC）布局。 形状可以由指定配置中的一组关联边界来定义。 定义了一个形状的目录，并且布局处理动作与各种形状相关联。 每个布局处理动作都对其关联的形状应用指定的布局修改。 基于形状的规则系统有利地实现了布局修改的有效配置和精确应用。 形状/动作可以作为默认值提供，可以从远程源检索，也可以由用户定义。 布局处理动作可以在偏置表中进行编译。 偏置表可以包括基于规则的和基于模型的动作，并且还可以包括单边形状以获得完整性。 IC布局的扫描可以按照增加或减少的复杂性的顺序执行，或者可以由用户指定。 将适当的布局处理动作应用于IC布局的匹配部分以形成校正的光掩模布局。 此过程可以是顺序或批处理模式。 形状和行动冲突可以通过标记识别/修改的元素或通过设计规则来解决，以有序地解决任何不一致或重叠。
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公开(公告)号：US07483559B2
公开(公告)日：2009-01-27
申请号：US10917942
申请日：2004-08-13
IPC分类号： G06K9/00
CPC分类号： G06T5/003 , G06T5/20 , G06T2207/20008 , G06T2207/20056 , G06T2207/20081
摘要： The invention comprises processes for determining and applying a deblurring filter that reduces inspection system distortion, of mask inspection images, by compensating for the non-uniform frequency response of the inspection system.In particular, an adaptive filter is determined empirically for an inspection system: one or more training images are obtained by the inspection system and the filter is determined from such images. In this way, the filter can adapt to the characteristics of each individual inspection system.An example adaptive filter, known as a Weiner filter, is determined and applied.
摘要翻译： 本发明包括通过补偿检查系统的不均匀频率响应来确定和应用减少检查系统失真的掩模检查图像的去模糊滤波器的方法。 特别地，对于检查系统经验地确定自适应滤波器：由检查系统获得一个或多个训练图像，并且根据这些图像确定滤波器。 以这种方式，过滤器可以适应每个检测系统的特性。 确定并应用称为维纳滤波器的示例自适应滤波器。
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