公开(公告)号：US20110084325A1

公开(公告)日：2011-04-14

申请号：US12649361

申请日：2009-12-30

Applicant: Hsiao-Lei Wang ,  Chung-Lin Huang ,  Hung-Chang Liao ,  Shih-Lung Chen

Inventor： Hsiao-Lei Wang ,  Chung-Lin Huang ,  Hung-Chang Liao ,  Shih-Lung Chen

IPC: H01L27/108 ,  H01L21/762

CPC classification number: H01L27/10894 ,  H01L21/76229 ,  H01L27/10897

Abstract: An oxide spacer for stack DRAM gate stack is described, including: a semiconductor substrate with a memory array region and a periphery region, a plurality of gates disposed within the memory array region and the periphery region respectively, a silicon oxide spacer disposed on the gates, where the polysilicon contact plugs are formed by polysilicon deposition and chemical mechanical polish. After polysilicon contact plugs are formed, a silicon oxide layer is deposited to isolate the contacts and gate. The silicon oxide layer on top of contact plug is removed by chemical mechanical polish achieve planarization.

Abstract translation: 描述了一种用于堆叠DRAM栅极堆叠的氧化物间隔物，包括：具有存储器阵列区域和外围区域的半导体衬底，分别设置在存储器阵列区域和外围区域内的多个栅极，设置在栅极上的氧化硅间隔物 其中多晶硅接触插塞通过多晶硅沉积和化学机械抛光形成。 在形成多晶硅接触塞之后，沉积氧化硅层以隔离触点和栅极。 通过化学机械抛光去除接触塞顶部的氧化硅层，实现平面化。

公开(公告)号：US07855124B2

公开(公告)日：2010-12-21

申请号：US12035529

申请日：2008-02-22

Applicant: Hung-Ming Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Ming Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/76

CPC classification number: H01L21/823437 ,  H01L21/28273 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/11521

Abstract: A method for forming a semiconductor device, includes the steps of providing a substrate; forming a patterned stack on the substrate including a first dielectric layer on the substrate, a first conductive layer on the first dielectric layer and a mask layer on the first conductive layer, wherein a width of the mask layer is smaller than a width of the first conductive layer; forming a second dielectric layer on the sidewall of the patterned stack; forming a third dielectric layer on the substrate; forming a second conductive layer over the substrate; and removing the mask layer and a portion of the first conductive layer covered by the mask layer to form an opening so as to partially expose the first conductive layer.

Abstract translation: 一种形成半导体器件的方法，包括以下步骤：提供衬底; 在所述衬底上形成图案化的叠层，所述衬底上包括在所述衬底上的第一电介质层，所述第一电介质层上的第一导电层和所述第一导电层上的掩模层，其中所述掩模层的宽度小于所述第一导电层的宽度 导电层; 在所述图案化叠层的侧壁上形成第二电介质层; 在所述基板上形成第三电介质层; 在所述衬底上形成第二导电层; 以及去除所述掩模层和由所述掩模层覆盖的所述第一导电层的一部分以形成开口以部分地暴露所述第一导电层。

公开(公告)号：US20100279499A1

公开(公告)日：2010-11-04

申请号：US12839387

申请日：2010-07-19

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/8247

CPC classification number: H01L27/11521

Abstract: A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.

Abstract translation: 一种用于制造存储器的方法，包括首先提供具有水平相邻的控制栅极区域和浮置栅极区域的衬底，该栅极区域包括牺牲层和牺牲侧壁，去除牺牲层和牺牲侧壁以露出衬底，形成邻近控制的电介质侧壁 栅极区域，在暴露的衬底上形成浮栅电介质层，并形成与电介质侧壁相邻的浮栅极和浮置栅极电介质层。

公开(公告)号：US07781804B2

公开(公告)日：2010-08-24

申请号：US12101164

申请日：2008-04-11

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/80

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: A non-volatile memory disposed on a substrate includes active regions, a memory array, and contacts. The active regions defined by isolation structures disposed in the substrate are extended in a first direction. The memory array is disposed on the substrate and includes memory cell columns, control gate lines and select gate lines. Each of the memory cell columns includes memory cells connected to one another in series and a source/drain region disposed in the substrate outside the memory cells. The contacts are disposed on the substrate at a side of the memory array and arranged along a second direction. The second direction crosses over the first direction. Each of the contacts extends across the isolation structures and connects the source/drain regions in the substrate at every two of the adjacent active regions.

Abstract translation: 设置在基板上的非易失性存储器包括有源区，存储器阵列和触点。 由设置在基板中的隔离结构限定的有源区域沿第一方向延伸。 存储器阵列设置在衬底上，并且包括存储单元列，控制栅极线和选择栅极线。 每个存储单元列包括彼此串联的存储单元和设置在存储单元外部的衬底中的源/漏区。 触点在存储器阵列的一侧设置在衬底上，并沿第二方向布置。 第二个方向穿过第一个方向。 每个触点延伸穿过隔离结构，并且在每个相邻的活性区域的每两个处连接衬底中的源极/漏极区域。

公开(公告)号：US20100013062A1

公开(公告)日：2010-01-21

申请号：US12244295

申请日：2008-10-02

Applicant: Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L23/58 ,  H01L21/31

CPC classification number: H01L27/11521 ,  H01L21/3185 ,  H01L29/42324 ,  H01L29/66825

Abstract: A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed.

Abstract translation: 提供非易失性存储单元。 提供半导体衬底。 导电层和间隔层顺序地设置在半导体衬底之上。 在导电层和间隔层中限定具有底部和多个侧表面的至少一个沟槽。 第一氧化物层形成在沟槽的底部。 在第一氧化物层，间隔层和沟槽的多个侧表面上形成介电层。 在沟槽中形成第一多晶硅层。 并且去除间隔层上的电介质层的第一部分，从而形成用于非易失性存储单元的基本结构。

公开(公告)号：US20090061581A1

公开(公告)日：2009-03-05

申请号：US11945199

申请日：2007-11-26

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/336

CPC classification number: H01L29/7887 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

Abstract: A method for manufacturing a non-volatile memory is provided. An isolation structure is formed in a trench formed in a substrate. A portion of the isolation structure is removed to form a recess. A first dielectric layer and a first conductive layer are formed sequentially on the substrate. Bar-shaped cap layers are formed on the substrate. The first conductive layer not covered by the bar-shaped cap layers is removed to form first gate structures. A second dielectric layer is formed on the sidewalls of the first gate structures. A third dielectric layer is formed on the substrate between the first gate structures. A second conductive layer is formed on the third dielectric layer. The bar-shaped cap layers and a portion of the first conductive layer are removed to form second gate structures. A doped region is formed in the substrate at two sides of each of the second gate structures.

Abstract translation: 提供一种用于制造非易失性存储器的方法。 在衬底中形成的沟槽中形成隔离结构。 去除隔离结构的一部分以形成凹部。 在基板上依次形成第一介电层和第一导电层。 在基板上形成棒状盖层。 未被棒状帽层覆盖的第一导电层被去除以形成第一栅极结构。 在第一栅极结构的侧壁上形成第二介电层。 在第一栅极结构之间的衬底上形成第三电介质层。 在第三电介质层上形成第二导电层。 条形盖层和第一导电层的一部分被去除以形成第二栅极结构。 在每个第二栅极结构的两侧在衬底中形成掺杂区域。

公开(公告)号：US20080305593A1

公开(公告)日：2008-12-11

申请号：US11949786

申请日：2007-12-04

Applicant: Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

Inventor： Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

IPC: H01L21/336

CPC classification number: H01L27/11534 ,  H01L21/84 ,  H01L27/11526 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887

Abstract: A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.

Abstract translation: 本发明公开的存储器结构的特征在于控制栅极和位于凹槽中的浮栅。 一种制造存储器结构的方法包括以下步骤：首先提供具有第一凹槽的衬底。 然后，在第一凹槽上形成第一栅极电介质层。 第一导电层形成在第一栅极介电层上。 之后，蚀刻第一导电层以形成用作第一凹槽的侧壁上的浮动栅极的间隔物。 在第一凹槽的底部形成第二凹槽。 在间隔物的表面，第二凹槽的侧壁和底部上形成栅极间电介质层。 形成为填充第一和第二凹槽的第二导电层。

公开(公告)号：US20080283897A1

公开(公告)日：2008-11-20

申请号：US11857978

申请日：2007-09-19

Applicant: Yu-Sheng Ding ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Yu-Sheng Ding ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/4983 ,  H01L21/28061 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/4933 ,  H01L29/66545 ,  H01L29/7887

Abstract: The invention provides a flash memory device and a method for fabricating thereof. The device comprises a gate stack layer of a gate dielectric layer and a gate polysilicon layer formed on a substrate, a stack layer comprising a floating polysilicon layer and gate spacer formed on the sidewall of the gate stack layer. A metal layer is formed on the gate stack layer and is utilized in place of a portion of the gate polysilicon layer. Because the metal layer has relatively high conductivity and is electrically connected to a metal plug later formed, current velocity of the device is increased to improve performance.

Abstract translation: 本发明提供一种闪存器件及其制造方法。 该器件包括形成在衬底上的栅极电介质层和栅极多晶硅层的栅极堆叠层，包括形成在栅极堆叠层的侧壁上的浮置多晶硅层和栅极间隔区的堆叠层。 在栅叠层上形成金属层，代替栅极多晶硅层的一部分。 因为金属层具有较高的导电性并且电连接到稍后形成的金属塞上，因此提高了器件的电流速度以提高性能。

公开(公告)号：US20080095411A1

公开(公告)日：2008-04-24

申请号：US11603031

申请日：2006-11-22

Applicant: Wen-Liang Hwang ,  Jian-Liang Lin ,  Chung-Lin Huang ,  Wei-Gang Che

Inventor： Wen-Liang Hwang ,  Jian-Liang Lin ,  Chung-Lin Huang ,  Wei-Gang Che

IPC: G06K9/00

CPC classification number: G06K9/0061

Abstract: The present invention disclose an iris recognition method, which utilizes a matching pursuit algorithm to simplify the extraction and reconstruction of iris features and reduce the memory space required by each iris feature vector without the penalty of recognition accuracy. The iris recognition method of the present invention comprises an iris-localization component and a pattern matching component. The iris-localization component locates the iris region via the color difference between different portions of the eyeball. The primary iris features are extracted from iris information and transformed into a sequence of iris feature vectors by a matching pursuit algorithm. Thus, the iris image can be represented by a sequence of atoms, and each atom contains base, amplitude and location. Then, the comparison between the feature vectors of two irises is performed to determine whether the two irises match.

Abstract translation: 本发明公开了一种虹膜识别方法，其利用匹配追踪算法来简化虹膜特征的提取和重建，并减少每个虹膜特征向量所需的存储空间，而不会损失识别精度。 本发明的虹膜识别方法包括虹膜定位部件和图案匹配部件。 虹膜定位组件经由眼球的不同部分之间的色差定位虹膜区域。 主要虹膜特征从虹膜信息中提取，并通过匹配追踪算法转换成虹膜特征向量序列。 因此，虹膜图像可以由原子序列表示，并且每个原子包含基底，幅度和位置。 然后，执行两个虹膜的特征向量之间的比较，以确定两个虹膜是否匹配。

公开(公告)号：US06486032B1

公开(公告)日：2002-11-26

申请号：US10174672

申请日：2002-06-18

Applicant: Chih-Hui Lin ,  Chung-Lin Huang

Inventor： Chih-Hui Lin ,  Chung-Lin Huang

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

Abstract: A method for fabricating the control gate and floating gate of a flash memory cell. An active area is firstly formed on a semiconductor substrate, followed by the formation of a first insulating layer, a first conductive layer and a first masking layer. A first opening is then formed by partially removing the first masking layer, and a floating gate oxide layer is formed by oxidation. The remaining first masking layer is removed, followed by forming a sacrificial layer, which is then partially removed to define a second opening. The remaining sacrificial layer is used as a hard mask to partially remove the first conductive layer and the first insulating layer to form a third opening. A second insulating layer is formed to fill the third opening to form an insulating plug. Part of the first conductive layer and the first insulating layer are removed to form a floating gate, followed by forming a third insulating layer and a second conductive layer. The insulating plug is then used as stop layer to remove part of the second conductive layer and third insulating layer to form a control gate.

Abstract translation: 一种用于制造闪存单元的控制栅极和浮置栅极的方法。 首先在半导体衬底上形成有源区，然后形成第一绝缘层，第一导电层和第一掩模层。 然后通过部分去除第一掩模层形成第一开口，并且通过氧化形成浮栅氧化层。 除去剩余的第一掩蔽层，随后形成牺牲层，然后部分地去除牺牲层以限定第二开口。 剩余的牺牲层用作硬掩模以部分地去除第一导电层和第一绝缘层以形成第三开口。 形成第二绝缘层以填充第三开口以形成绝缘插头。 去除第一导电层和第一绝缘层的一部分以形成浮置栅极，随后形成第三绝缘层和第二导电层。 然后将绝缘插头用作停止层以去除部分第二导电层和第三绝缘层以形成控制栅极。