公开(公告)号：US20040221130A1

公开(公告)日：2004-11-04

申请号：US10834994

申请日：2004-04-30

Inventor： Jui Yang Lai ,  Hsin Ching Yin

IPC: G06F012/08

CPC classification number: G06F12/0292 ,  G06F2212/2022

Abstract: A method for accessing a non-volatile memory by both PC and X-BOX is disclosed. The method includes the following steps: initializing a memory controller, preferably with a USB interface, for accessing the non-volatile memory; generating the first logical-to-physical address mapping table for mapping the first portion of the non-volatile memory; configuring the controller; monitoring the occurrence of an event; analyzing the starting logic address specified in a token packet sent from the host to the controller in response to the event; and generating the second logical-to-physical address mapping table for mapping the second portion of the non-volatile memory when its starting logic address is absent in the first logical-to-physical address mapping table.

Abstract translation: 公开了一种通过PC和X-BOX访问非易失性存储器的方法。 该方法包括以下步骤：初始化优选用USB接口的存储器控​​制器，用于访问非易失性存储器; 生成用于映射非易失性存储器的第一部分的第一逻辑到物理地址映射表; 配置控制器; 监测事件的发生; 分析从主机发送到控制器的令牌包中指定的启动逻辑地址以响应该事件; 以及当第一逻辑到物理地址映射表中的起始逻辑地址不存在时，生成用于映射非易失性存储器的第二部分的第二逻辑到物理地址映射表。

公开(公告)号：US20040221128A1

公开(公告)日：2004-11-04

申请号：US10712218

申请日：2003-11-13

Applicant: Quadrics Limited

Inventor： Jon Beecroft ,  David Hewson ,  Moray McLaren

IPC: G06F012/08

CPC classification number: G06F12/1018 ,  G06F12/1027 ,  G06F12/1072 ,  G06F2212/652

Abstract: A computer network (1) comprises:- a plurality of processing nodes, at least two of which each having respective addressable memories and respective network interfaces (2); and a switching network (3) which operatively connects the plurality of processing nodes together, each network interface (2) including a memory management unit (8a) having associated with it a memory in which is stored (a) at least one mapping table for mapping 64 bit virtual addresses to the physical addresses of the addressable memory of the respective processing node; and (b) instructions for applying a compression algorithm to said virtual addresses, the at least one mapping table comprising a plurality of virtual addresses and their associated physical addresses ordered with respect to compressed versions of the 64 bit virtual addresses. The network interface (2) provides visibility across the network of areas of the memory of individual processing nodes in a way which supports full scalability of the network.

Abstract translation: 计算机网络（1）包括： - 多个处理节点，其中至少两个具有各自的可寻址存储器和相应的网络接口（2）; 以及将所述多个处理节点可操作地连接在一起的交换网络（3），每个网络接口（2）包括与其相关联的存储器的存储器管理单元（8a），其中存储有（a）至少一个映射表， 将64位虚拟地址映射到相应处理节点的可寻址存储器的物理地址; 以及（b）用于将压缩算法应用于所述虚拟地址的指令，所述至少一个映射表包括关于64位虚拟地址的压缩版本排序的多个虚拟地址及其相关联的物理地址。 网络接口（2）以支持网络的完全可扩展性的方式提供各个处理节点的存储器区域的网络的可见性。

公开(公告)号：US20040221127A1

公开(公告)日：2004-11-04

申请号：US10693147

申请日：2003-10-23

Inventor： Boon Seong Ang

IPC: G06F012/08

CPC classification number: G06F12/126 ,  G06F12/1027 ,  G06F12/1081

Abstract: A memory system and a set of user-level instructions that are callable from user-level code for converting virtual addresses to physical addresses and conveying the physical addresses to peripheral devices without requiring a system call. The system uses a translation look-aside buffer (TLB) implemented in a microprocessor. The contents of the TLB can be updated while processes are executing, allowing for virtual/physical addresses to be constantly updated and loaded into the buffer without requiring that the buffer be too large. Pages in use per transaction or user-level job are nullpinned downnull and pinned page counts per transaction or user-level job, as well as overall counts are maintained.

Abstract translation: 存储系统和一组用户级指令，可从用户级代码调用，用于将虚拟地址转换为物理地址，并将物理地址传送到外围设备，而无需系统调用。 该系统使用在微处理器中实现的翻译后备缓冲器（TLB）。 TLB的内容可以在进程执行时更新，允许虚拟/物理地址不断更新并加载到缓冲区中，而不需要缓冲区太大。 每个交易或用户级作业中使用的页面都被“固定”，每个事务或用户级作业的固定页数，以及总计数保持不变。

公开(公告)号：US20040221110A1

公开(公告)日：2004-11-04

申请号：US10861638

申请日：2004-06-04

Inventor： Joseph B. Rowlands ,  Michael P. Dickman

IPC: G06F012/08

CPC classification number: G06F12/126 ,  G06F12/121

Abstract: A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a way of the cache. The cache may alter the state of its replacement policy in response to a direct access transaction explicitly specifying a particular way of the cache. The state may be altered such that a succeeding cache miss causes an eviction of the particular way. Thus, a direct access transaction may be used to provide a deterministic setting to the replacement policy, providing predictability to the entry selected to store a subsequent cache miss. In one embodiment, the replacement policy may be a pseudo-random replacement policy. In one embodiment, a direct access transaction also explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions). Other embodiments may set the replacement policy based on other types of transactions.

公开(公告)号：US20040215919A1

公开(公告)日：2004-10-28

申请号：US10420979

申请日：2003-04-22

Applicant: International Business Machines Corporation

Inventor： David B. Emmes

IPC: G06F012/08

CPC classification number: G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/656

Abstract: A method and apparatus for managing shared virtual storage in an information handling system in which each of a plurality of processes managed by an operating system has a virtual address space comprising a range of virtual addresses that are mapped to a corresponding set of real addresses representing addresses in real storage. The virtual address spaces are 64-bit address spaces requiring up to five levels of dynamic address translation (DAT) tables to map their virtual addresses to real addresses. One or more shared ranges of virtual addresses are defined that are mapped for each of a plurality of virtual address spaces to a common set of real addresses. The operating system manages these shared ranges using a system-level DAT table that reference a shared set of DAT tables used by the sharing address spaces for address translation, but is not attached to the hardware address translation facilities or used for address translation. The shared range of virtual addresses straddles the 242-byte boundary between ranges served by different third-level DAT tables and is situated between a lower private range and an upper private range so that an individual address space can map both a lower private range and a shared range using only three levels of DAT tables. Each shared address range may be shared with either global access rights, in which each participating process has the same access rights, or local access rights in which each participant may have different access rights to the given range. Access rights for each participant may be changed over the lifetime of the process.

Abstract translation: 一种用于在信息处理系统中管理共享虚拟存储的方法和装置，其中由操作系统管理的多个进程中的每一个具有虚拟地址空间，该虚拟地址空间包括被映射到表示地址的对应的一组真实地址的虚拟地址范围 在真正的存储。 虚拟地址空间是64位地址空间，最多需要五层动态地址转换（DAT）表，以将其虚拟地址映射到实际地址。 定义虚拟地址的一个或多个共享范围，其被映射到多个虚拟地址空间中的每个虚拟地址空间到一组共同的真实地址。 操作系统使用引用共享地址空间用于地址转换的共享DAT表集合的系统级DAT表管理这些共享范围，但不附加到硬件地址转换工具或用于地址转换。 虚拟地址的共享范围跨越由不同的第三级DAT表服务的范围之间的2个42字节边界，并且位于较低的专用范围和较高的专用范围之间，使得单个地址空间可以映射较低的私有 范围和仅使用三个级别的DAT表的共享范围。 每个共享地址范围可以与全局访问权限共享，每个参与进程具有相同的访问权限，或者每个参与者可以具有给定范围的不同访问权限的本地访问权限。 每个参与者的访问权限可以在该过程的整个生命周期内更改。

公开(公告)号：US20040215907A1

公开(公告)日：2004-10-28

申请号：US10422215

申请日：2003-04-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Travis James Pizel ,  Thomas Rembert Sand ,  William Alan Thompson

IPC: G06F012/14 ,  G06F012/08

CPC classification number: G06F12/1475 ,  G06F12/109 ,  H04L47/10 ,  H04L47/18 ,  H04L47/39

Abstract: A method, apparatus, system, and signal-bearing medium that in an embodiment pre-register buffers remotely and create tokens locally that represent the buffers prior to a data transfer operation that uses the tokens to access the buffers. In an embodiment, the buffers are pre-registered via a translation table, and the tokens are used as an offset into the translation table. In an embodiment, the pre-registration verifies that the buffer is within memory allocated to a logical partition, which protects against the risk of address corruption.

Abstract translation: 一种方法，装置，系统和信号承载介质，其在一个实施例中预先寄存缓冲器，并且在使用令牌访问缓冲器的数据传送操作之前本地创建代表缓冲器的令牌。 在一个实施例中，缓冲器经由转换表预先登记，并且令牌被用作到转换表中的偏移量。 在一个实施例中，预注册验证缓冲器在分配给逻辑分区的存储器内，其防止地址损坏的风险。

公开(公告)号：US20040215883A1

公开(公告)日：2004-10-28

申请号：US10831248

申请日：2004-04-23

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Roger J. Bamford ,  Sashikanth Chandrasekaran ,  Angelo Pruscino

IPC: G06F012/08

CPC classification number: G06F17/3048 ,  G06F12/0871 ,  G06F12/0893 ,  Y10S707/99952

Abstract: Various techniques are described for improving the performance of a multiple node system by allocating, in two or more nodes of the system, partitions of a shared cache. A mapping is established between the data items managed by the system, and the various partitions of the shared cache. When a node requires a data item, the node first determines which partition of the shared cache corresponds to the required data item. If the data item does not currently reside in the corresponding partition, the data item is loaded into the corresponding partition even if the partition does not reside on the same node that requires the data item. The node then reads the data item from the corresponding partition of the shared cache.

Abstract translation: 描述了各种技术，用于通过在系统的两个或更多个节点中分配共享高速缓存的分区来提高多节点系统的性能。 在系统管理的数据项和共享缓存的各个分区之间建立映射。 当节点需要数据项时，节点首先确定共享缓存的哪个分区对应于所需的数据项。 如果数据项当前不在相应的分区中，则即使分区不在需要数据项的同一节点上，数据项也会被加载到相应的分区中。 然后，节点从共享高速缓存的相应分区读取数据项。

公开(公告)号：US20040215882A1

公开(公告)日：2004-10-28

申请号：US10424487

申请日：2003-04-25

Applicant: International Business Machines Corp.

Inventor： Gregory William Alexander ,  David Stephen Levitan ,  Balaram Sinharoy

IPC: G06F012/08

CPC classification number: G06F12/0864 ,  G06F12/1054 ,  G06F2212/6082

Abstract: A set-associative I-cache that enables early cache hit prediction and correct way selection when the processor is executing instructions of multiple threads having similar EAs. Each way of the I-cache comprises an EA Directory (EA Dir), which includes a series of thread valid bits that are individually assigned to one of the multiple threads. Particular ones of the thread valid bits are set in each EA Dir to indicate when an instruction block the thread is cached within the particular way with which the EA Dir is associated. When a cache line request for a particular thread is received, a cache hit is predicted when the EA of the request matches the EA in the EA Dir and the cache line is selected from the way associated with the EA Dir who has the thread valid bit for that thread set. Early way selection is thus achieved since the way selection only requires a check of the thread valid bits.

Abstract translation: 当处理器执行具有类似EA的多个线程的指令时，能够实现早期缓存命中预测和正确选择方法的集合关联I缓存。 I缓存的每个方式包括EA目录（EA目录），其包括单独分配给多个线程之一的一系列线程有效位。 在每个EA Dir中设置特定的线程有效位，以指示线程是否以EA Dir所关联的特定方式缓存的时间。 当接收到针对特定线程的高速缓存线请求时，当请求的EA与EA Dir中的EA匹配时，预测缓存命中，并且从与具有线程有效位的EA Dir相关联的方式中选择高速缓存行 为该线程集。 因此，由于选择方式仅需要检查线程有效位，因此实现了早期方式选择。

公开(公告)号：US20040215876A1

公开(公告)日：2004-10-28

申请号：US10422921

申请日：2003-04-23

Inventor： Paolo F. Roberti

IPC: G06F012/08

CPC classification number: G06F12/126 ,  G06F12/0866

Abstract: A method and system for improving the performance of a processing system is disclosed. The processing system comprises a plurality of host computers, at least one control unit (CU) coupled to the host computer. The control unit comprises a cache and disk array coupled to the CU. The method and system comprises querying an operating system of at least one host computer to determine the storage medium that contains an object to be cached and providing the data in the portion of the disk array to be cached. The method and system further comprises providing a channel command sequence and sending the channel command sequence to the CU via an I/O operation at predetermined time intervals until the object is deactivated. A method and system in accordance with the present invention instructs a control unit (CU) or a storage medium to keep some objects constantly in its cache, so as to improve the overall response time of transaction systems running on one or more host computer and accessing data on disk via the CU.

Abstract translation: 公开了一种用于提高处理系统的性能的方法和系统。 处理系统包括多个主机计算机，耦合到主计算机的至少一个控制单元（CU）。 控制单元包括耦合到CU的高速缓存和磁盘阵列。 所述方法和系统包括：查询至少一台主机的操作系统，以确定包含要缓存的对象的存储介质，并提供要缓存的磁盘阵列部分中的数据。 所述方法和系统还包括提供信道命令序列，并且以预定的时间间隔经由I / O操作向CU发送信道命令序列，直到对象被去激活为止。 根据本发明的方法和系统指示控制单元（CU）或存储介质将一些对象持续保持在其高速缓存中，以便改善在一个或多个主计算机上运行的事务系统的总响应时间并访问 通过CU在磁盘上的数据。

公开(公告)号：US20040210708A1

公开(公告)日：2004-10-21

申请号：US10841388

申请日：2004-05-07

Inventor： Kevin M. Conley

IPC: G06F012/08

CPC classification number: G11C16/102 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06F2212/7209 ,  G11C16/105 ,  G11C2216/16

Abstract: Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.

Abstract translation: 通过对相同或另一块的未使用页面中的新数据进行编程来更新少于非易失性存储器块的所有页面中的数据。 为了防止不必要将不变的数据页复制到新的块中，或者将标记编程到被替换的数据页面中，新数据的页面被与它们所取代的数据页面相同的逻辑地址标识，并且时间戳 当每个页面被写入时都会添加注释。 当读取数据时，将使用最新的数据页面，并忽略较旧的旧版数据页面。 通过将所有页面更新指向一个单元中的单个未使用的块，该技术也应用于包含来自存储器阵列的几个不同单元中的每一个的一个块的元区块。