Circuit board mounting support
    1.
    发明授权

    公开(公告)号:US12022615B2

    公开(公告)日:2024-06-25

    申请号:US17939659

    申请日:2022-09-07

    IPC分类号: H05K1/14

    CPC分类号: H05K1/144 H05K2201/042

    摘要: A circuit board mounting support for supporting a first electronic circuit integration includes a bearing member. The first electronic circuit integration includes a circuit board, an electronic component engaged with a first surface of the circuit board, and multiple legs for engaging with the bearing member. The circuit board has a mounting area for mounting the electronic component and a second surface opposite to the first surface. The bearing member includes a groove and an engaging portion connected to a peripheral edge of the groove. A corresponding area is defined on the bearing member and corresponds to the mounting area of the circuit board. When the bearing member is engaged with the circuit board, an opening of the groove and the engaging portion face the second surface. A junction that each of the legs is engaged with the bearing member is located out of the corresponding area.

    NETWORK SWITCH AND CIRCUIT BOARD WHERE PRECISION TIME PROTOCOL MODULE IS USED

    公开(公告)号:US20230171016A1

    公开(公告)日:2023-06-01

    申请号:US17993986

    申请日:2022-11-24

    发明人: Kuan-Tse Lee

    IPC分类号: H04J3/06

    CPC分类号: H04J3/0667 H04J3/0641

    摘要: A network switch can include a precision time protocol (PTP) module and a circuit board. The PTP module can provide a first clock signal and include a predetermined interface. The circuit board can include a socket, an oscillator and a selection unit. The socket can be inserted by the predetermined interface to receive the first clock signal. The oscillator can provide a second clock signal. The selection unit can include a first terminal, a second terminal, an output terminal and a selection terminal. The first terminal can receive the first clock signal when the predetermined interface is inserted into the socket. The second terminal can receive the second clock signal. The output terminal can output one of the first clock signal and the second clock signal. The selection terminal can receive a selection signal to control the output terminal to output the first clock signal or the second clock signal.

    NETWORK SWITCH INCLUDING TRANSMISSION PORTS WHICH ARE NOT ARRANGED TOWARD A SAME DIRECTION

    公开(公告)号:US20230140400A1

    公开(公告)日:2023-05-04

    申请号:US17978179

    申请日:2022-10-31

    发明人: Kuan-Tse Lee

    IPC分类号: H05K1/02

    摘要: A network switch includes a circuit board and a plurality of transmission ports. The circuit board is disposed in a chassis, and an opening of the chassis is corresponding to a first reference line. The plurality of transmission ports are disposed on an edge of the circuit board. The edge is corresponding to a second reference line, and the first reference line and the second reference line form an acute angle.

    NETWORK DEVICE
    5.
    发明申请

    公开(公告)号:US20220060311A1

    公开(公告)日:2022-02-24

    申请号:US17444909

    申请日:2021-08-11

    IPC分类号: H04L7/00

    摘要: A network device adapted for sending a synchronization packet to a slave device. The synchronization packet includes a timestamp field and a correction field. The network device includes a counting circuit, a communication chip, and a processor. The counting circuit is configured to provide a calendar time TOD. The communication chip includes a first port, a second port, and a timestamp circuit which has a bit number N. The processor is coupled to the first port of the communication chip. The processor is configured to: obtain a remainder R according to the calendar time TOD and the bit number N; and write the calendar time TOD and the remainder R into the synchronization packet.

    Time synchronization device and time synchronization method

    公开(公告)号:US11177896B2

    公开(公告)日:2021-11-16

    申请号:US16655261

    申请日:2019-10-17

    IPC分类号: H04J3/06

    摘要: A time synchronization device performs a time synchronization process with a device that provides first and second time values. The time synchronization device includes a packet processing circuit, a time counting circuit, and a processor. The packet processing circuit includes a timestamp counter having an N-bit length, and the packet processing circuit provides first to third time counting values. The processor calculates the first offset value based on the first and second time values and the first and second time counting values; calculates the first adjustment value based on the first offset value and the reciprocal of the frequency of the time counting circuit; calculates a second quotient value and a second remainder value based on the first adjustment value and the N-bit length; and calculates the receiving time of the second synchronization packet based on the N-bit length, the second quotient value, and the third time counting value.

    WIRELESS ACCESS POINT DEVICE
    7.
    发明申请

    公开(公告)号:US20210242573A1

    公开(公告)日:2021-08-05

    申请号:US17148519

    申请日:2021-01-13

    发明人: Chih-Chang HSIEH

    摘要: A wireless access point device includes a main frame, a transmission assembly, an antenna module and a fixing assembly. The main frame includes a casing and a first connection portion connected to the casing. The transmission assembly is disposed in an internal space of the casing and provided with a signal transceiving element. The antenna module includes a waveguide, a second connection portion and a positioning recess. The second connection portion is disposed on the waveguide and detachably connected to the first connection portion to be coupled to the signal transceiving element. The positioning recess is formed on the second connection portion. The fixing assembly is movably disposed on the first connection portion. The antenna module is thereby fixed on the casing, when the second connection portion and the first connection portion are fixed through the fixing assembly removably inserting into the positioning recess.

    Network interface cards, fabric cards, and line cards for loop avoidance in a chassis switch

    公开(公告)号:US11075834B2

    公开(公告)日:2021-07-27

    申请号:US16181935

    申请日:2018-11-06

    发明人: Chin-Chieh Huang

    IPC分类号: H04L12/937 H04L12/705

    摘要: A network interface card installed in a chassis switch, which includes a switch device and a controller, is provided. The switch device includes a plurality of ports coupled to other network interface cards in the chassis switch, and each of the other network interface cards is a fabric card or a line card. The controller is configured to perform different acts according to the card type of the network interface card, wherein the acts constitute a specific process of path planning which may prevent loops from occurring in the communication paths of control packet delivery between multiple network interface cards in the chassis switch.

    Waterproof assembly
    9.
    发明授权

    公开(公告)号:US10749290B2

    公开(公告)日:2020-08-18

    申请号:US16529824

    申请日:2019-08-02

    发明人: Chih-Chang Hsieh

    IPC分类号: H01R13/52

    摘要: A waterproof assembly includes a casing, a gasket, and a cap. The casing has an opening. The gasket includes a main body and a protruding portion. The main body has a first circular raised structure configured to abut against an inner surface of the casing. The protruding portion is connected to the main body and is configured to at least partially protrude out of the casing through the opening. The cap is configured to abut against a side of the main body away from the opening. The cap has a through hole configured to be aligned with the protruding portion. The casing further has a plurality of fixing members configured to abut against a side of the cap away from the gasket.

    PCI express network card
    10.
    发明授权

    公开(公告)号:US10248603B2

    公开(公告)日:2019-04-02

    申请号:US15210774

    申请日:2016-07-14

    发明人: Cheng-Che Hsieh

    摘要: A PCI Express network card is disclosed, including a circuit board, a plate, a plurality of integrated circuits, and two heat sinks. The circuit board has five ports. The plate is provided on the circuit board and near a front edge of the circuit board, wherein the plate has a plurality of openings. The integrated circuits are provided on the circuit board, including a first processor and a second processor, which consume the most power. The first processor and the second processor are arranged in a staggered way. Each of the heat sinks abuts against the first processor and the second processor, respectively. An area of each of the heat sinks is greater than an area of each one of the first processor and the second processor. Whereby, effective heat dissipation could be achieved.