Virtual path merging in a multipoint-to-point network tunneling protocol
    1.
    发明授权
    Virtual path merging in a multipoint-to-point network tunneling protocol 失效
    虚拟路径合并在多点到点网络隧道协议中

    公开(公告)号:US06967955B1

    公开(公告)日:2005-11-22

    申请号:US09534737

    申请日:2000-03-27

    摘要: A computer network includes frame- or packet-based subnetworks connected by switches, the switches being interconnected by high-capacity trunks using a connection-based data transfer protocol similar to Asynchronous Transfer Mode (ATM). Some of the trunks include a Permanent Virtual Path (PVP) trunk crossing an ATM core network, the PVP trunk including one or more bidirectional PVPs. A multipoint-to-point (MPT) protocol is used among the switches to transfer packets as groups of cells directly from “leaf”, or source, switches to “root”, or destination, switches without requiring significant routing-related processing during cell transmission. The switches allocate virtual path identifiers in a conserving manner such that (i) MPT paths from multiple leaf switches are merged to one path with a single virtual path identifier terminating at a root switch; (ii) on the PVP trunks, a virtual path identifier already allocated for an outgoing connection is allocated to an incoming connection ahead of any virtual path identifiers that are completely unallocated; and (iii) a range of virtual path identifiers is pre-provisioned at the core network access points, so that a switch connected to an access point allocates virtual path identifiers from the pre-provisioned range on behalf of upstream switches to extend MPTs across the core network.

    摘要翻译: 计算机网络包括由交换机连接的基于帧或分组的子网络,这些交换机使用类似于异步传输模式(ATM)的基于连接的数据传输协议由大容量中继器互连。 一些中继线包括穿过ATM核心网络的永久虚拟路径(PVP)中继线,PVP中继线包括一个或多个双向PVP。 交换机之间使用多点对点(MPT)协议,将数据包作为一组数据单元直接从“叶”或“源”切换到“根”或目的地交换机,而不需要在单元格期间进行明显的路由相关处理 传输。 交换机以保守的方式分配虚拟路径标识符,使得(i)来自多个叶交换机的MPT路径被合并到具有终止于根交换机的单个虚拟路径标识符的一个路径; (ii)在PVP干线上,已经为出站连接分配的虚拟路径标识符被分配给完全未分配的任何虚拟路径标识符之前的传入连接; 并且(iii)虚拟路径标识符的范围在核心网络接入点预先配置,使得连接到接入点的交换机代表上游交换机从预先设定的范围分配虚拟路径标识符,以跨越 核心网络。

    Card cage accommodating PC cards of different size
    2.
    发明授权
    Card cage accommodating PC cards of different size 失效
    卡笼可容纳不同尺寸的PC卡

    公开(公告)号:US6008995A

    公开(公告)日:1999-12-28

    申请号:US924473

    申请日:1997-08-19

    IPC分类号: G06F1/18 H05K7/14

    摘要: A card cage for mounting printed circuit cards of at least two sizes is disclosed. The card cage includes an insert removably mounted to a mounting bar position between first and second ends of the card cage. The insert extends along a portion of the width of the card cage. When the insert is mounted to the mounting bar, a printed circuit card of a first length may be disposed between the insert and one of the card cage ends. When the insert is removed, a printed circuit card of a second length greater than the first length may be mounted between the first and second ends of the card cage. Plural mounting bars may be located between the respective card cage ends to accommodate printed circuit cards of different lengths.

    摘要翻译: 公开了一种用于安装至少两种尺寸的印刷电路卡的卡笼。 卡笼包括可移除地安装到卡笼的第一和第二端之间的安装杆位置的插入件。 插入件沿着卡笼的宽度的一部分延伸。 当插入件安装到安装杆上时,第一长度的印刷电路卡可以设置在插入件与卡盒端部中的一个之间。 当移除插入件时,大于第一长度的第二长度的印刷电路卡可以安装在卡盒的第一和第二端之间。 多个安装杆可以位于相应的卡笼端之间,以适应不同长度的印刷电路卡。

    Control processor switchover for a telecommunications switch
    3.
    发明授权
    Control processor switchover for a telecommunications switch 失效
    控制处理器切换电信交换机

    公开(公告)号:US5953314A

    公开(公告)日:1999-09-14

    申请号:US919828

    申请日:1997-08-28

    IPC分类号: G06F11/20 H04Q3/545 G06F13/00

    摘要: First and second control processor cards are employed in conjunction with first and second switch fabric cards to interconnect Input/Output cards in a telecommunications switch. The control processor cards provide a portion of the functionality previously associated with switch fabric cards, such as exertion of control over allocation of bandwidth within the switch. The control processor cards also provide new functionality. In particular, each control processor card can configure both switch fabric cards. Redundant control processor cards and redundant switch fabric cards are employed to provide a switch that is less susceptible to failure than switches with only redundant switch fabric cards. Hence, failure of a control processor card and a switch fabric card can be sustained without resulting in switch failure. Timing control functions may also be provided by a separate timing module card.

    摘要翻译: 第一和第二控制处理器卡与第一和第二交换结构卡结合使用以互连电信交换机中的输入/输出卡。 控制处理器卡提供先前与交换结构卡相关联的功能的一部分,例如对交换机内的带宽分配的控制。 控制处理器卡还提供新的功能。 特别地,每个控制处理器卡可以配置两个交换矩阵卡。 冗余控制处理器卡和冗余交换矩阵卡被用于提供一个不仅仅具有冗余交换矩阵卡的交换机的故障易受影响的交换机。 因此,可以维持控制处理器卡和交换矩阵卡的故障,而不会导致开关故障。 定时控制功能也可以由单独的定时模块卡提供。

    High speed packet scheduling method and apparatus
    4.
    发明授权
    High speed packet scheduling method and apparatus 失效
    高速分组调度方法及装置

    公开(公告)号:US5905730A

    公开(公告)日:1999-05-18

    申请号:US49510

    申请日:1998-03-27

    摘要: A packet scheduler is disclosed which provides a high degree of fairness in scheduling packets associated with different sessions. The scheduler also minimizes packet delay for packet transmission from a plurality of sessions which may have different requirements and may operate at different transfer rates. When a packet is received by the scheduler, the packet is assigned its own packet virtual start time based on whether the session has any pending packets and the values of the virtual finish time of the previous packet in the session and the packets arrival time. The scheduler then determines a virtual finish time of the packet by determining the transfer time required for the packet based upon its length and rate and by adding the transfer time to the packet virtual start time of the packet. The packet with the smallest virtual finish time is then scheduled for transfer. By selecting packets for transmission in the above described manner, the available bandwidth may be shared in pro-rata proportion to the guaranteed session rate, thereby providing a scheduler with a high degree of fairness while also minimizing the amount of time a packet waits in the scheduler before being served.

    摘要翻译: 公开了一种在调度与不同会话相关联的分组中提供高度公平性的分组调度器。 调度器还使来自可能具有不同要求并且可以以不同传送速率操作的多个会话的分组传输的分组延迟最小化。 当调度器接收到分组时,基于会话是否具有任何未决分组以及会话中的先前分组的虚拟完成时间的值和分组到达时间,向分组分配其自己的分组虚拟开始时间。 调度器然后通过基于其长度和速率确定分组所需的传送时间,并通过将传送时间添加到分组的分组虚拟开始时间来确定分组的虚拟完成时间。 然后计划传输最小虚拟完成时间的数据包。 通过以上述方式选择用于传输的分组,可以按照保证会话速率的比例共享可用带宽,从而提供高度公平的调度器,同时最小化分组等待的时间量 服务前调度程序。

    Virtual path merging in a multipoint-to-point network tunneling protocol
    5.
    发明授权
    Virtual path merging in a multipoint-to-point network tunneling protocol 失效
    虚拟路径合并在多点到点网络隧道协议中

    公开(公告)号:US6097726A

    公开(公告)日:2000-08-01

    申请号:US074364

    申请日:1998-05-07

    摘要: A computer network includes frame- or packet-based subnetworks connected by switches, the switches being interconnected by high-capacity trunks using a connection-based data transfer protocol similar to Asynchronous Transfer Mode (ATM). Some of the trunks include a Permanent Virtual Path (PVP) trunk crossing an ATM core network, the PVP trunk including one or more bidirectional PVPs. A multipoint-to-point (MPT) protocol is used among the switches to transfer packets as groups of cells directly from "leaf", or source, switches to "root", or destination, switches without requiring significant routing-related processing during cell transmission. The switches allocate virtual path identifiers in a conserving manner such that (i) MPT paths from multiple leaf switches are merged to one path with a single virtual path identifier terminating at a root switch; (ii) on the PVP trunks, a virtual path identifier already allocated for an outgoing connection is allocated to an incoming connection ahead of any virtual path identifiers that are completely unallocated; and (iii) a range of virtual path identifiers is pre-provisioned at the core network access points, so that a switch connected to an access point allocates virtual path identifiers from the pre-provisioned range on behalf of upstream switches to extend MPTs across the core network.

    摘要翻译: 计算机网络包括由交换机连接的基于帧或分组的子网络,这些交换机使用类似于异步传输模式(ATM)的基于连接的数据传输协议由大容量中继器互连。 一些中继线包括穿过ATM核心网络的永久虚拟路径(PVP)中继线,PVP中继线包括一个或多个双向PVP。 交换机之间使用多点对点(MPT)协议,将数据包作为一组数据单元直接从“叶”或“源”切换到“根”或目的地交换机,而不需要在单元格期间进行明显的路由相关处理 传输。 交换机以保守的方式分配虚拟路径标识符,使得(i)来自多个叶交换机的MPT路径被合并到具有终止于根交换机的单个虚拟路径标识符的一个路径; (ii)在PVP干线上,已经为出站连接分配的虚拟路径标识符被分配给完全未分配的任何虚拟路径标识符之前的传入连接; 并且(iii)虚拟路径标识符的范围在核心网络接入点预先配置,使得连接到接入点的交换机代表上游交换机从预先设定的范围分配虚拟路径标识符,以跨越 核心网络。

    Timing synchronization and switchover in a network switch
    6.
    发明授权
    Timing synchronization and switchover in a network switch 失效
    网络交换机中的定时同步和切换

    公开(公告)号:US6078595A

    公开(公告)日:2000-06-20

    申请号:US920250

    申请日:1997-08-28

    IPC分类号: H04J3/06 H04Q11/04

    CPC分类号: H04Q11/0421 H04J3/0688

    摘要: A data communications switch and method of operation are presently disclosed enabling flexible, selectable provision of a common timing signal for synchronized external communication through physical layer interfaces with other network devices, synchronized internal communications within the switch, and for uninterrupted synchronization of such communications. Synchronization of external communications is enabled by programmable selection from among plural potential timing references at redundant timing modules (TMs). An active TM provides a primary external synchronization clock; a standby TM provides a redundant timing function. Both TMs access the same references. A state signal indicates which synchronization clock is active. External interfaces derive timing from this distributed clock. Synchronized internal timing is provided by an internal clock and phase-locked loop (PLL) on each TM. The clock/PLL timing signal output is routed to other switch elements, enabling synchronized internal data transfer. Both interconnected TMs actively generate clock signals for external and internal use, enabling seamless timing switchover should conditions warrant a change in TMs.

    摘要翻译: 目前公开了一种数据通信开关和操作方法,使得能够灵活地,可选择地提供用于通过与其他网络设备的物理层接口同步的外部通信,交换机内的同步内部通信以及这种通信的不间断同步的公共定时信号。 通过在冗余定时模块(TM)的多个潜在定时参考中的可编程选择来实现外部通信的同步。 主动TM提供主要的外部同步时钟; 备用TM提供冗余定时功能。 两个TM都访问相同的引用。 状态信号指示哪个同步时钟是活动的。 外部接口从该分布式时钟导出时序。 同步的内部时序由每个TM上的内部时钟和锁相环(PLL)提供。 时钟/ PLL定时信号输出被路由到其他开关元件,实现同步的内部数据传输。 两个互连的TM主动地产生用于外部和内部使用的时钟信号,如果条件需要TM变化,则实现无缝时序切换。

    Virtual private network system and method
    7.
    发明授权
    Virtual private network system and method 失效
    虚拟专网系统及方法

    公开(公告)号:US6055575A

    公开(公告)日:2000-04-25

    申请号:US13122

    申请日:1998-01-26

    IPC分类号: H04L29/06 H04L29/12 G06F13/00

    摘要: A system and method for remote users to access a private network having a first communications protocol via a public network, such as any TCP/IP network having a second different communications protocol, in a secure manner so that the remote user appears to be connected directly to the private network and appears to be a node on that private network. A host connected to the private network may execute a host software application which establishes and provides a communications path for secure access of the remote client computer. An encrypted data stream may be communicated between the host and the client representing traffic and commands on the network.

    摘要翻译: 远程用户以安全的方式通过公共网络(诸如具有第二不同通信协议的任何TCP / IP网络)访问具有第一通信协议的私有网络的系统和方法,使得远程用户看起来直接连接 到专用网络,并且似乎是该专用网络上的节点。 连接到专用网络的主机可以执行主机软件应用程序,其建立并提供用于远程客户端计算机的安全访问的通信路径。 可以在主机和表示网络上的业务和命令的客户端之间传送加密的数据流。

    System and method for processing data packets
    8.
    发明授权
    System and method for processing data packets 失效
    用于处理数据包的系统和方法

    公开(公告)号:US6032190A

    公开(公告)日:2000-02-29

    申请号:US943512

    申请日:1997-10-03

    IPC分类号: H04L12/56 G06F13/00

    摘要: An apparatus and method for processing a data packet to determine the routing of the data packet through a communications network is provided in which the data packet has a header portion and a data portion. The apparatus stores the header portion of the data packet, and processes the header portion of the data packet. The processing may include using a processing core for executing instructions for processing the header portion, searching through a route table to determine a route of the data packet, and searching through a table memory for information about the destination of the data packet in which the route table search, the table memory search and the processing core operate simultaneously to process the header portion and generate an internal header or a network media header. A modified header portion is generated to route the data packet through the communications network. A method for processing data packets to determine the route of the data packet is also provided in which a header portion is received from an incoming data packet, an search based on the received header portion is performed, a route look-up search is performed, and the information contained within the header portion is processed simultaneously for determining if the header portion is valid and generating an internal header or network media header based on the results of the route look-up search, the interface search, and other processing.

    摘要翻译: 提供了一种用于处理数据分组以通过通信网络确定数据分组的路由的装置和方法,其中数据分组具有头部部分和数据部分。 该装置存储数据分组的报头部分,并处理数据分组的报头部分。 该处理可以包括使用处理核来执行用于处理报头部分的指令,通过路由表搜索来确定数据分组的路由,以及通过表存储器搜索关于其中路由的数据分组的目的地的信息 表搜索,表存储器搜索和处理核同时操作以处理标题部分并生成内部报头或网络媒体报头。 生成修改的报头部分以通过通信网络路由数据分组。 还提供了一种用于处理数据分组以确定数据分组的路由的方法,其中从输入数据分组接收报头部分,执行基于所接收的报头部分的搜索,执行路由查找搜索, 并且包含在头部部分中的信息被同时处理,以便确定头部部分是否有效,并且基于路线查找搜索,接口搜索和其他处理的结果来生成内部头部或网络媒体头部。

    Electronic interconnection method and apparatus for minimizing
propagation delays
    9.
    发明授权
    Electronic interconnection method and apparatus for minimizing propagation delays 失效
    用于最小化传播延迟的电子互连方法和装置

    公开(公告)号:US6015300A

    公开(公告)日:2000-01-18

    申请号:US919825

    申请日:1997-08-28

    摘要: A module interconnection system which minimizes electronic signal propagation delays is disclosed. The module interconnection system includes a backplane, a first plurality of connectors arranged in a side by side generally parallel arrangement, and a second plurality of connectors arranged in a side by side generally parallel arrangement. In a preferred embodiment, the second plurality of connectors are mounted on the backplane at right angles to the first plurality of connectors so as provide short routing paths between each of the second plurality of connectors and at least one of the first plurality of connectors. Point-to-point signal interconnections are selectively utilized to provide data paths between selected contacts of at least one of the first plurality of connectors and selected contacts of the second plurality of connectors. The above described interconnection apparatus permits high speed data communication between modules disposed in at least one of said first plurality of connectors and at least one module disposed in said second plurality of connectors.

    摘要翻译: 公开了使电子信号传播延迟最小化的模块互连系统。 模块互连系统包括背板,并排布置为大致平行布置的第一多个连接器和大体平行布置并排布置的第二多个连接器。 在优选实施例中,第二多个连接器以与第一多个连接器成直角的方式安装在背板上,从而在第二多个连接器中的每一个与第一多个连接器中的至少一个之间提供短路由路径。 点对点信号互连被选择性地用于在第一多个连接器中的至少一个连接器和第二多个连接器的选定触点之间的选定触点之间提供数据路径。 上述互连装置允许设置在所述第一多个连接器中的至少一个中的模块和设置在所述第二多个连接器中的至少一个模块之间的高速数据通信。