公开(公告)号：US10306516B2

公开(公告)日：2019-05-28

申请号：US15438823

申请日：2017-02-22

Applicant: Ceva D.S.P. Ltd.

Inventor： David Levy

IPC: H04W28/22 ,  H04L29/06 ,  H03M13/27 ,  H03M13/29 ,  H03M13/00 ,  H04L1/00

Abstract: A method and a logic circuit for rate matching for three equally sized bit streams, including: prepending each of the bit streams with null bits; permuting the first two bit streams according to a first permutation pattern; permuting the third bit stream based on the first permutation pattern; transposing the three bit streams; shuffling the second and third bit streams; removing the null bits from the first bit stream and from the shuffled bit stream, wherein location of the null bits in the first bit stream is based only on a number of prepended null bits and the first permutation pattern and location of the null bits in the shuffled bit stream is based only on the number of prepended null bits, the first permutation pattern, and a null index related to the number of prepended null bits; and generating a combined bit stream from the three bit streams.

公开(公告)号：US10169040B2

公开(公告)日：2019-01-01

申请号：US15352598

申请日：2016-11-16

Applicant: Ceva D.S.P. Ltd.

Inventor： Hagay Rozin ,  Jeffery Allan (Alon) Jacob (Yaakov)

IPC: G06F9/30 ,  G06F17/10

Abstract: A system and method for performing sample rate conversion by an execution unit, including receiving an instruction, where the instruction comprises an irregular shifting pattern of data elements stored in a vector register, and shifting the data elements in the vector register according to the irregular shifting pattern. In case of upsampling the irregular shifting pattern includes an indication stating whether a memory element loads a data element from an immediate next memory element or from a second next memory element. In case of downsampling the irregular shifting pattern includes an indication stating whether a memory element in the input vector register loads a data element from an immediate next memory element, or whether the memory element loads a data element previously stored in a shadow vector register and the data element stored in the immediate next memory element is loaded into the shadow vector register.

公开(公告)号：US09977601B2

公开(公告)日：2018-05-22

申请号：US15073103

申请日：2016-03-17

Applicant: Ceva D.S.P. Ltd.

Inventor： Hagay Rozin ,  Jeffrey Allan (Alon) Jacob (Yaakov)

IPC: G06F3/06 ,  H03H17/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  H03H17/0223 ,  H03H17/06

Abstract: A system and method for symmetrical filtering of an input string may include loading, into at least one vector register, in a single read cycle, a subset of right-side data elements and a subset of left-side data elements of the input string. The input string may be stored sequentially in a memory unit. The right-side data elements and the left-side data elements may be equally distant from the center of the input string and may be separated by a whole number of rows in the memory. The system and method may include performing filtering of the input string using a symmetrical filter with the loaded right-side data elements and left-side data elements.

公开(公告)号：US09009410B2

公开(公告)日：2015-04-14

申请号：US13215298

申请日：2011-08-23

Applicant: Amos Rohe ,  Alex Shlezinger

Inventor： Amos Rohe ,  Alex Shlezinger

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F12/126 ,  G06F12/0815 ,  G06F2212/1016 ,  Y10S707/99938

Abstract: A system and method for locking data in a cache memory. A first processing thread may be operated to run a program requesting data, where at least some of the requested data is loaded from a source memory into a non-empty cache. A second processing thread may be operated independently of the first processing thread to determine whether or not to lock the requested data in the cache. If the requested data is determined to be locked, the requested data may be locked in the cache at the same time as the data is loaded into the cache.

Abstract translation: 用于将数据锁定在高速缓冲存储器中的系统和方法。 可以操作第一处理线程以运行请求数据的程序，其中所请求的数据中的至少一些被从源存储器加载到非空高速缓存。 可以独立于第一处理线程操作第二处理线程，以确定是否将所请求的数据锁定在高速缓存中。 如果所请求的数据被确定为被锁定，则所请求的数据可以在数据被加载到高速缓存中的同时被锁定在高速缓存中。

公开(公告)号：US08320690B2

公开(公告)日：2012-11-27

申请号：US12797727

申请日：2010-06-10

Applicant: Jeffrey Allan (Alon) Jacob (Yaakov)

Inventor： Jeffrey Allan (Alon) Jacob (Yaakov)

IPC: G06K9/36

CPC classification number: G06T1/60

Abstract: A system, processor, and method for processing multiple dimension data. A single rectangular data array having a single data port may store a set of data elements representing a multi-dimensional pixel array. A load/store unit may receive the set of data elements and store them divided among a plurality of individually addressable data arrays each having separate address ports. Each individually addressable data array may include at most a single row that stores data elements from a sub-set of the set of data elements representing a multi-dimensional sub-array of the pixel array. A processor may simultaneously access the single row of each of the plurality of individually addressable data arrays by accessing the corresponding respective address ports for each individually addressable data array to retrieve the complete sub-set of data elements in a single computational cycle. An execution unit may execute instruction(s) on the sub-set of data elements.

Abstract translation: 一种用于处理多维数据的系统，处理器和方法。 具有单个数据端口的单个矩形数据阵列可以存储表示多维像素阵列的一组数据元素。 加载/存储单元可以接收该组数据元素并将它们存储在各自具有单独的地址端口的多个可单独寻址的数据阵列之间。 每个可单独寻址的数据阵列可以包括最多一行，其存储来自表示像素阵列的多维子阵列的数据元素组的子集的数据元素。 处理器可以通过访问用于每个可单独寻址的数据阵列的相应的相应地址端口来同时访问多个可单独寻址的数据阵列中的每一个的单行，以在单个计算周期内检索完整的数据元素子集。 执行单元可以在数据元素子集上执行指令。

公开(公告)号：US08213502B2

公开(公告)日：2012-07-03

申请号：US11967288

申请日：2007-12-31

Applicant: Eldad Melamed ,  Roni M. Sadeh ,  Erez Barniv

Inventor： Eldad Melamed ,  Roni M. Sadeh ,  Erez Barniv

IPC: G06K9/36

CPC classification number: H04N19/194 ,  H04N19/124 ,  H04N19/137 ,  H04N19/139 ,  H04N19/176 ,  H04N19/182 ,  H04N19/196 ,  H04N19/197 ,  H04N19/61

Abstract: A system and method for controlling video compression quantization comprising generating a quantizer scale offset based on diagonal frequencies of luminance components of a data block samples, luminance intensity of the samples and motion activity of the data block, adjusting a first quantizer scale using the quantizer scale offset to receive a second quantizer scale and quantizing the data block using the second quantizer scale.

Abstract translation: 一种用于控制视频压缩量化的系统和方法，包括基于数据块样本的亮度分量，样本的亮度强度和数据块的运动活动的对角频率生成量化器尺度偏移，使用量化器尺度调整第一量化器尺度 偏移以接收第二量化器比例并且使用第二量化器比例量化数据块。

公开(公告)号：US07467332B2

公开(公告)日：2008-12-16

申请号：US11055974

申请日：2005-02-14

Applicant: Gil Drori ,  Erez Bar-Niv ,  David Dahan ,  Omir Eisenbach

Inventor： Gil Drori ,  Erez Bar-Niv ,  David Dahan ,  Omir Eisenbach

IPC: G06F11/00

CPC classification number: G06F11/3648

Abstract: A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.

Abstract translation: 一种具有至少一个断点生成模块和用于向计算设备中的至少一个断点生成模块和核心处理器提供相互断点能力的核心处理器和方法的系统。 每个断点产生模块能够产生用于允许核心处理器和每个断点产生模块的操作停止的第一断点消息。 第二个断点消息允许停止核心处理器的操作。 第二个断点消息对应于第一个断点消息。 此外，核心处理器产生第三个断点消息，用于允许核心处理器和每个断点生成模块的操作停止。

公开(公告)号：US20080052460A1

公开(公告)日：2008-02-28

申请号：US11931833

申请日：2007-10-31

Applicant: Gil DRORI ,  Erez Bar Niv ,  David Dahan

Inventor： Gil DRORI ,  Erez Bar Niv ,  David Dahan

IPC: G06F12/00

CPC classification number: G06F13/28

Abstract: A method and system for transferring data in a multi ordered memory array from a source memory array to a destination memory array, at least one of which is multi-ordered. A reading memory access unit reads data from the source memory array according to a source access template and a writing memory access unit writes the data to the destination memory array according to a destination access template.

Abstract translation: 一种用于将多序存储器阵列中的数据从源存储器阵列传送到目的地存储器阵列的方法和系统，其中至少一个是多次排序的。 读取存储器访问单元根据源访问模板从源存储器阵列读取数据，并且写入存储器存取单元根据目的地访问模板将数据写入目的地存储器阵列。

公开(公告)号：US20060085684A1

公开(公告)日：2006-04-20

申请号：US11055974

申请日：2005-02-14

Applicant: Gil Drori ,  Erez Bar-Niv ,  David Dahan ,  Omri Eisenbach

Inventor： Gil Drori ,  Erez Bar-Niv ,  David Dahan ,  Omri Eisenbach

IPC: G06F11/00

CPC classification number: G06F11/3648

Abstract: A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.

Abstract translation: 一种具有至少一个断点生成模块和用于向计算设备中的至少一个断点生成模块和核心处理器提供相互断点能力的核心处理器和方法的系统。 每个断点产生模块能够产生用于允许核心处理器和每个断点产生模块的操作停止的第一断点消息。 第二个断点消息允许停止核心处理器的操作。 第二个断点消息对应于第一个断点消息。 此外，核心处理器产生第三个断点消息，用于允许核心处理器和每个断点生成模块的操作停止。

公开(公告)号：US06868186B1

公开(公告)日：2005-03-15

申请号：US09615774

申请日：2000-07-13

Applicant: Roni M. Sadeh

Inventor： Roni M. Sadeh

IPC: H04N11/04 ,  G06T9/00 ,  H03M7/30 ,  H03M7/36 ,  H03M7/40 ,  H04N1/41 ,  H04N7/26 ,  H04N7/30 ,  H04N7/32 ,  G06K9/00 ,  G06K9/36 ,  G06K9/46

CPC classification number: H04N19/186 ,  H04N19/60

Abstract: An image compression method is provided including separating an image into a plurality of color channel sub-images processing each of the color channel sub-images by sub-sampling the sub-image transform coding the sub-sampled sub-image decoding the transform-coded image forming a plurality of square groupings of pixels in the decoded image predicting a value for a pixel within each of the x-shaped groupings determining a prediction error for each predicted pixel value within each of the square groupings coding the prediction error forming a plurality of at least partly diamond-shaped groupings of pixels in the decoded image predicting a value for a pixel within each of the diamond-shaped groupings and combining each of the processed color channel sub-images with the coded prediction errors, thereby forming a compressed image.

Abstract translation: 提供了一种图像压缩方法，包括：通过对对每个彩色通道子图像进行处理的多个彩色通道子图像进行子采样，对经过变换编码的子采样子图像进行解码， 在所述解码图像中形成多个正方形分像像素的图像，所述图像中的每一个中的每个所述x形分组中的像素的值确定在编码预测误差的每个所述正方形分组内的每个预测像素值的预测误差，形成多个 所述解码图像中的至少部分菱形像素分组预测每个所述菱形分组内的像素的值，并将所述经处理的色道子图像中的每一个与所述编码的预测误差组合，由此形成压缩图像。