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1.发明授权Time and frequency synchronization method for OFDMA uplink receivers and base stations 有权OFDMA上行接收机和基站的时频同步方法公开(公告)号：US08514774B2
公开(公告)日：2013-08-20
申请号：US11676914
申请日：2007-02-20
Applicant: Yiqun Ge , Wuxian Shi , Juan Du
Inventor： Yiqun Ge , Wuxian Shi , Juan Du
CPC classification number: H04L27/2657 , H04L27/2662 , H04L27/2684 , H04L27/2691
Abstract: A method, and components for performing such method, is provided for synchronizing multiple user signals in a multi-user communication system. An interference matrix is generated based on time delay and frequency offset information for the active users accessing an OFDMA uplink receiver. User signals are received from the active users and are segmented into blocks, and the interference matrix is applied to each of the blocks. The received user signal is OFDM demodulated and un-used sub-carriers are discarded. Typically, the method includes also applying a factorization matrix formed by factoring a correction matrix created from the interference matrix and an inverse matrix formed based on the factoring results to the user signal blocks, e.g., the correction step includes multiplying each of the blocks from the user signal by each of these three matrices. The corrected user blocks are then concatenated to form a corrected vector signal.
Abstract translation: 提供一种用于执行这种方法的方法和用于在多用户通信系统中同步多个用户信号的组件。 基于用于访问OFDMA上行链路接收机的活动用户的时间延迟和频率偏移信息生成干扰矩阵。 从活动用户接收用户信号，并将其分割为块，并且将干扰矩阵应用于每个块。 接收到的用户信号是OFDM解调的，未使用的子载波被丢弃。 通常，该方法还包括应用通过将从干扰矩阵产生的校正矩阵分解而形成的分解矩阵和基于因子分解结果形成的逆矩阵到用户信号块，例如，校正步骤包括将来自 用户信号通过这三个矩阵中的每一个。 校正的用户块然后被级联以形成校正的矢量信号。
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2.发明申请REGISTER FILE ORGANIZATION TO SHARE PROCESS CONTEXT FOR HETEROGENEOUS MULTIPLE PROCESSORS OR JOINT PROCESSOR 有权注册文件组织分享异构多处理器或联合处理器的过程公开(公告)号：US20130173865A1
公开(公告)日：2013-07-04
申请号：US13692744
申请日：2012-12-03
Inventor： YongQiang WU , PengFei ZHU , HongXia SUN , Elio GUIDETTI
IPC: G06F12/08
CPC classification number: G06F12/0802 , G06F9/30098 , G06F9/3012 , G06F9/30141
Abstract: A register file organization is used to support multiple accesses from more than one processor or pipeline. This shared register file is organized for a multiple processor device that includes a high performance (HP) and a low power (LP) core. The shared register file includes separate HP and LP storage units coupled to separate HP and LP write and read ports.
Abstract translation: 注册文件组织用于支持来自多个处理器或管道的多个访问。 该共享寄存器文件针对包含高性能（HP）和低功耗（LP）内核的多处理器设备进行组织。 共享寄存器文件包括单独的HP和LP存储单元，耦合到单独的HP和LP写入和读取端口。
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公开(公告)号：US08397148B2
公开(公告)日：2013-03-12
申请号：US13368190
申请日：2012-02-07
Applicant: Wuxian Shi , Juan Du , Yiqun Ge , Guobin Sun
Inventor： Wuxian Shi , Juan Du , Yiqun Ge , Guobin Sun
IPC: H03M13/03
CPC classification number: H03M13/3938 , H03M13/413 , H03M13/6362 , H03M13/6502 , H03M13/6505 , H04L1/0054 , H04L1/0059
Abstract: A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as infinity. The input bit stream is read and a Search Depth Viterbi algorithm (SDVA) is performed to determine path metrics and identify a minimum-metric path. The ending state for the minimum-metric path is determined and the output for this ending state is identified as “previous output.” A second starting state is set to the ending state of the minimum-metric path, and symbols equal to the correction depth from the previous output are read. The SDVA is performed on the second set of read symbols to generate a corrected output. A decoded output is generated by replacing symbols at the beginning of the previous output with the corrected output.
Abstract translation: 一种用于解码尾巴卷积码的方法。 该方法包括初始化校正深度，从一组编码状态中选择第一起始状态，以及将所选择的起始状态的度量值初始化为零，将其他状态初始化为无穷大。 读取输入比特流，执行搜索深度维特比算法（SDVA）以确定路径度量并识别最小度量路径。 确定最小度量路径的结束状态，将该结束状态的输出识别为先前的输出。 第二起始状态被设置为最小度量路径的结束状态，并且读取等于来自先前输出的校正深度的符号。 在第二组读符号上执行SDVA以产生校正输出。 通过使用校正输出替换先前输出开始处的符号来产生解码输出。
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4.发明授权Blind carrier frequency offset estimator based on single-OFDM-symbol PN ranging code in multi-user OFDMA uplink 有权基于多用户OFDMA上行链路中的单OFDM符号PN测距码的盲载波频偏估计器公开(公告)号：US07742392B2
公开(公告)日：2010-06-22
申请号：US11833157
申请日：2007-08-02
Applicant: Yiqun Ge , Xutao Zhou , Wuxian Shi
Inventor： Yiqun Ge , Xutao Zhou , Wuxian Shi
IPC: H04J11/00
CPC classification number: H04L27/2657 , H04L27/2676
Abstract: A blind carrier frequency offset estimator is based on a single-OFDM-symbol training sequence in multi-user OFDMA uplink. Through multiple access interference modeling and analysis, a virtual user is employed that occupies the all null sub-carriers. By minimizing the energy leakage on the virtual user in term of tentative frequency offsets, the estimator can approach the real frequency offset. The estimator performs only on frequency-domain, simplifies interference calculations, and lowers the rank of the matrix. An iterative computation method is used to approach the real frequency offset.
Abstract translation: 盲载波频偏估计器基于多用户OFDMA上行链路中的单OFDM符号训练序列。 通过多址干扰建模和分析，采用占用全部空子载波的虚拟用户。 通过最小化虚拟用户在暂定频率偏移方面的能量泄漏，估计器可以接近实际频率偏移。 估计器仅在频域上执行，简化了干扰计算，并降低了矩阵的秩。 迭代计算方法用于逼近实际频偏。
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5.发明申请TIME AND FREQUENCY SYNCHRONIZATION METHOD FOR OFDMA UPLINK RECEIVERS AND BASE STATIONS 有权OFDMA上网接收者和基站的时间和频率同步方法公开(公告)号：US20070202903A1
公开(公告)日：2007-08-30
申请号：US11676914
申请日：2007-02-20
Applicant: Yiqun Ge , Wuxian Shi , Juan Du
Inventor： Yiqun Ge , Wuxian Shi , Juan Du
IPC: H04B7/00
CPC classification number: H04L27/2657 , H04L27/2662 , H04L27/2684 , H04L27/2691
Abstract: A method, and components for performing such method, is provided for synchronizing multiple user signals in a multi-user communication system. An interference matrix is generated based on time delay and frequency offset information for the active users accessing an OFDMA uplink receiver. User signals are received from the active users and are segmented into blocks, and the interference matrix is applied to each of the blocks. The received user signal is OFDM demodulated and un-used sub-carriers are discarded. Typically, the method includes also applying a factorization matrix formed by factoring a correction matrix created from the interference matrix and an inverse matrix formed based on the factoring results to the user signal blocks, e.g., the correction step includes multiplying each of the blocks from the user signal by each of these three matrices. The corrected user blocks are then concatenated to form a corrected vector signal.
Abstract translation: 提供一种用于执行这种方法的方法和用于在多用户通信系统中同步多个用户信号的组件。 基于用于访问OFDMA上行链路接收机的活动用户的时间延迟和频率偏移信息生成干扰矩阵。 从活动用户接收用户信号，并将其分割为块，并且将干扰矩阵应用于每个块。 接收到的用户信号是OFDM解调的，未使用的子载波被丢弃。 通常，该方法还包括应用通过将从干扰矩阵产生的校正矩阵分解而形成的分解矩阵和基于因子分解结果形成的逆矩阵到用户信号块，例如，校正步骤包括将来自 用户信号通过这三个矩阵中的每一个。 校正的用户块然后被级联以形成校正的矢量信号。
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Patent Agency Ranking
6.发明授权Decoding method for tail-biting convolutional codes using a search depth viterbi algorithm 有权使用搜索深度维特比算法解码卷积码的解码方法公开(公告)号：US08136023B2
公开(公告)日：2012-03-13
申请号：US12945661
申请日：2010-11-12
Applicant: Wuxian Shi , Juan Du , Yiqun Ge , Guobin Sun
Inventor： Wuxian Shi , Juan Du , Yiqun Ge , Guobin Sun
IPC: H03M13/03
CPC classification number: H03M13/3938 , H03M13/413 , H03M13/6362 , H03M13/6502 , H03M13/6505 , H04L1/0054 , H04L1/0059
Abstract: A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as infinity. The input bit stream is read and a Search Depth Viterbi algorithm (SDVA) is performed to determine path metrics and identify a minimum-metric path. The ending state for the minimum-metric path is determined and the output for this ending state is identified as “previous output.” A second starting state is set to the ending state of the minimum-metric path, and symbols equal to the correction depth from the previous output are read. The SDVA is performed on the second set of read symbols to generate a corrected output. A decoded output is generated by replacing symbols at the beginning of the previous output with the corrected output.
Abstract translation: 一种用于解码尾巴卷积码的方法。 该方法包括初始化校正深度，从一组编码状态中选择第一起始状态，以及将所选择的起始状态的度量值初始化为零，将其他状态初始化为无穷大。 读取输入比特流，执行搜索深度维特比算法（SDVA）以确定路径度量并识别最小度量路径。 确定最小度量路径的结束状态，并将该结束状态的输出识别为“先前输出”。将第二起始状态设置为最小度量路径的结束状态，等于校正深度的符号 从以前的输出读取。 在第二组读符号上执行SDVA以产生校正输出。 通过使用校正输出替换先前输出开始处的符号来产生解码输出。
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7.发明授权Modified balanced throughput data-path architecture for special correlation applications 有权用于特殊相关应用的改进的平衡吞吐量数据路径架构公开(公告)号：US09424033B2
公开(公告)日：2016-08-23
申请号：US13936886
申请日：2013-07-08
Inventor： PengFei Zhu , HongXia Sun , YongQiang Wu , Elio Guidetti
CPC classification number: G06F9/3004 , G06F9/30043 , G06F9/30112 , G06F9/30127 , G06F9/345 , G06F9/3824 , G06F9/3893
Abstract: Apparatus and method for a modified, balanced throughput data-path architecture is given for efficiently implementing the digital signal processing algorithms of filtering, convolution and correlation in computer hardware, in which both data and coefficient buffers can be implemented as sliding windows. This architecture uses a multiplexer and a data path branch from the Address Generator unit to the multiply-accumulate execution unit. By selecting between the data path of Address Generator to execution unit and the data path of register to execution unit, the unbalanced throughput and multiply-accumulate bubble cycles caused by misaligned addressing on coefficients can be overcome. The modified balanced throughput data-path architecture can achieve a high multiply-accumulate operation rate per cycle in implementing digital signal processing algorithms.
Abstract translation: 给出了一种改进的平衡吞吐量数据路径架构的装置和方法，用于有效实现计算机硬件中过滤，卷积和相关的数字信号处理算法，其中数据和系数缓冲器都可以实现为滑动窗口。 该架构使用从地址发生器单元到乘法累加执行单元的多路复用器和数据路径分支。 通过在地址发生器到执行单元的数据通路与寄存器到执行单元的数据通路之间进行选择，可以克服由不对称寻址对系数引起的不平衡吞吐量和乘法累加气泡循环。 改进的平衡吞吐量数据路径架构在实现数字信号处理算法时可以实现每个周期的高乘法累加运算速率。
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公开(公告)号：US20120137198A1
公开(公告)日：2012-05-31
申请号：US13368190
申请日：2012-02-07
Applicant: Wuxian Shi , Juan Du , Yigun Ge , Guobin Sun
Inventor： Wuxian Shi , Juan Du , Yigun Ge , Guobin Sun
CPC classification number: H03M13/3938 , H03M13/413 , H03M13/6362 , H03M13/6502 , H03M13/6505 , H04L1/0054 , H04L1/0059
Abstract: A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as infinity. The input bit stream is read and a Search Depth Viterbi algorithm (SDVA) is performed to determine path metrics and identify a minimum-metric path. The ending state for the minimum-metric path is determined and the output for this ending state is identified as “previous output.” A second starting state is set to the ending state of the minimum-metric path, and symbols equal to the correction depth from the previous output are read. The SDVA is performed on the second set of read symbols to generate a corrected output. A decoded output is generated by replacing symbols at the beginning of the previous output with the corrected output.
Abstract translation: 一种用于解码尾巴卷积码的方法。 该方法包括初始化校正深度，从一组编码状态中选择第一起始状态，以及将所选择的起始状态的度量值初始化为零，将其他状态初始化为无穷大。 读取输入比特流，执行搜索深度维特比算法（SDVA）以确定路径度量并识别最小度量路径。 确定最小度量路径的结束状态，并将该结束状态的输出识别为“先前输出”。将第二起始状态设置为最小度量路径的结束状态，等于校正深度的符号 从以前的输出读取。 在第二组读符号上执行SDVA以产生校正输出。 通过使用校正输出替换先前输出开始处的符号来产生解码输出。
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9.发明授权Data accessing method to boost performance of FIR operation on balanced throughput data-path architecture 有权数据访问方法，以提高平衡吞吐量数据路径架构上FIR操作的性能公开(公告)号：US09082476B2
公开(公告)日：2015-07-14
申请号：US13936849
申请日：2013-07-08
Inventor： PengFei Zhu , HongXia Sun , YongQiang Wu , Elio Guidetti
CPC classification number: G11C19/00 , G06F9/3001 , G06F9/30036 , G06F9/3004 , G06F9/3012 , G06F9/3887 , G06F9/3891 , G06F9/3893
Abstract: An apparatus and method are disclosed to implement digital signal processing operations involving multiply-accumulate (MAC) operations, by using a modified balanced data structure and accessing architecture. This architecture maintains a data-path connecting one address generation unit, one register file and one MAC execution unit. The register file has a hierarchical grouping organization of individual registers, which reduces bubble cycles caused by memory misalignments. This architecture uses parallel execution and can achieve two or more MAC operations per cycle.
Abstract translation: 公开了一种通过使用修改的平衡数据结构和访问架构来实现涉及乘法累加（MAC）操作的数字信号处理操作的装置和方法。 该架构维护连接一个地址生成单元，一个寄存器文件和一个MAC执行单元的数据路径。 寄存器文件具有各个寄存器的分层分组组织，可以减少由于存储器未对准而导致的气泡循环。 该架构使用并行执行，并且可以在每个周期中实现两个或更多个MAC操作。
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10.发明申请DECODING METHOD FOR TAIL-BITING CONVOLUTIONAL CODES USING A SEARCH DEPTH VITERBI ALGORITHM 有权使用搜索深度维特比算法解码转换代码的解码方法公开(公告)号：US20070245209A1
公开(公告)日：2007-10-18
申请号：US11687543
申请日：2007-03-16
Applicant: Wuxian SHI , Juan DU , Yiqun GE , Guobin SUN
Inventor： Wuxian SHI , Juan DU , Yiqun GE , Guobin SUN
IPC: H03M13/00
CPC classification number: H03M13/3938 , H03M13/413 , H03M13/6362 , H03M13/6502 , H03M13/6505 , H04L1/0054 , H04L1/0059
Abstract: A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as infinity. The input bit stream is read and a Search Depth Viterbi algorithm (SDVA) is performed to determine path metrics and identify a minimum-metric path. The ending state for the minimum-metric path is determined and the output for this ending state is identified as “previous output.” A second starting state is set to the ending state of the minimum-metric path, and symbols equal to the correction depth from the previous output are read. The SDVA is performed on the second set of read symbols to generate a corrected output. A decoded output is generated by replacing symbols at the beginning of the previous output with the corrected output.
Abstract translation: 一种用于解码尾巴卷积码的方法。 该方法包括初始化校正深度，从一组编码状态中选择第一起始状态，以及将所选择的起始状态的度量值初始化为零，将其他状态初始化为无穷大。 读取输入比特流，执行搜索深度维特比算法（SDVA）以确定路径度量并识别最小度量路径。 确定最小度量路径的结束状态，将该结束状态的输出识别为“先前输出”。 第二起始状态被设置为最小度量路径的结束状态，并且读取等于来自先前输出的校正深度的符号。 在第二组读符号上执行SDVA以产生校正输出。 通过使用校正输出替换先前输出开始处的符号来产生解码输出。
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