公开(公告)号：US20060279305A1

公开(公告)日：2006-12-14

申请号：US11275768

申请日：2006-01-27

申请人： Dae Kyoung KIM ,  Sun Whan KIM ,  Dal Jo LEE

发明人： Dae Kyoung KIM ,  Sun Whan KIM ,  Dal Jo LEE

IPC分类号： G01R31/02

CPC分类号： G01R31/2889

摘要： The present invention relates to a semiconductor test interface for interfacing a DUT (Device Under Test) to a pin card using a cable comprising a DUT board including one or more first connectors for electrically connecting one or more test sockets for mounting the DUT to the one or more cables, and a circuit wiring for electrically connecting the one or more test sockets to the one or more first connectors; and the one more cable including a second connector for an electrical connection to the one or more first connectors, and a third connector for an electrical connection to the pin card, wherein the one or more first connectors correspond to the one or more cables by 1:1. In accordance with the present invention, the manufacturing cost is reduced by simplifying the manufacturing process and the semiconductor test interface may easily correspond to the test of the different DUTs.

摘要翻译： 本发明涉及一种半导体测试接口，用于使用包括DUT板的电缆将DUT（被测设备）连接到针卡，该电缆包括一个或多个第一连接器，用于将一个或多个测试插座电连接以将DUT安装到一个 或更多的电缆，以及用于将所述一个或多个测试插座电连接到所述一个或多个第一连接器的电路布线; 并且所述另一个电缆包括用于与所述一个或多个第一连接器的电连接的第二连接器和用于与所述销卡的电连接的第三连接器，其中所述一个或多个第一连接器对应于所述一个或多个电缆1 ：1。 根据本发明，通过简化制造过程来降低制造成本，并且半导体测试接口可以容易地对应于不同DUT的测试。

公开(公告)号：US20060242468A1

公开(公告)日：2006-10-26

申请号：US11295607

申请日：2005-12-07

申请人： Jong Kang

发明人： Jong Kang

IPC分类号： G06F11/00

CPC分类号： G11C29/56 ,  G11C5/04 ,  G11C29/56016

摘要： The present invention relates to a memory application tester for testing a semiconductor memory device comprising a plurality of motherboards having a memory socket. The motherboards are vertically mounted and effectively integrated so that a memory application tester may test more memory device simultaneously, and a limit in the trace length due to the integration of the motherboards is effectively solved.

摘要翻译： 本发明涉及一种用于测试包括具有存储器插座的多个母板的半导体存储器件的存储器应用测试器。 主板垂直安装并有效地集成，使得存储应用测试器可以同时测试更多的存储器，并且有效地解决了由于主板的集成而导致的迹线长度的限制。

公开(公告)号：US07327151B2

公开(公告)日：2008-02-05

申请号：US11295607

申请日：2005-12-07

申请人： Jong Koo Kang

发明人： Jong Koo Kang

IPC分类号： G01R31/02

CPC分类号： G11C29/56 ,  G11C5/04 ,  G11C29/56016

摘要： Disclosed is a memory application tester for testing a semiconductor memory device. A plurality of motherboards of the tester are vertically mounted and connected to memory devices to be tested mounted on an interface board via a HiFix board so that a memory application tester may test more memory device simultaneously, and a limit in the trace length due to the integration of the motherboards is effectively solved.

摘要翻译： 公开了一种用于测试半导体存储器件的存储器应用测试器。 测试仪的多个主板通过HiFix板垂直安装并连接到要测试的待测试的存储器件，以便存储器应用测试器可以同时测试更多的存储器件，并且由于 主板的整合得到有效的解决。

公开(公告)号：US20060109017A1

公开(公告)日：2006-05-25

申请号：US11281365

申请日：2005-11-18

申请人： Bong Kim ,  Kukjin Chun ,  Doo Chung ,  Chi Jeong

发明人： Bong Kim ,  Kukjin Chun ,  Doo Chung ,  Chi Jeong

IPC分类号： G01R31/02

CPC分类号： G01R1/07342 ,  G01R3/00

摘要： The present invention relates to a probe card that a probe of the probe card is movable only in a vertical direction using a trench to improve a electrical or a mechanical characteristic and to automatically limit the vertical movement thereof within a predetermined range. A pitch may be reduced so as to correspond to a decreasing distance between pads. A flatness of a probe tip may be maintained within a few micrometers using a semiconductor manufacturing process. 32 simultaneous parallel testing is possible contrary to a convention probe card. A wafer level testing is possible, and time and cost for a wafer testing are reduced.

摘要翻译： 本发明涉及一种探针卡，探针卡的探针仅在垂直方向上可以使用沟槽移动以改善电或机械特性，并且将其垂直移动限制在预定范围内。 间距可以减小以对应于垫之间的减小的距离。 使用半导体制造工艺可以将探针尖端的平坦度保持在几微米内。 32个同时并行测试可能与常规探针卡相反。 晶圆级测试是可能的，晶片测试的时间和成本降低。

公开(公告)号：US06883128B2

公开(公告)日：2005-04-19

申请号：US10214846

申请日：2002-08-08

申请人： Jong-Gu Kang ,  Jong-Hyun Kim

发明人： Jong-Gu Kang ,  Jong-Hyun Kim

IPC分类号： G01R31/26 ,  G11C29/56 ,  G06F11/00

CPC分类号： G11C29/56004 ,  G11C29/56

摘要： The present invention relates to a test equipment of a chip memory device. A memory pattern test is implemented using a pattern generation substrate in which a processor is designed in an EPLD for thereby implementing a PC test and pattern programming, so that a test evaluated under a PC environment formed of a CPU and chip sets. Two processes of a chip device test and automatic test are performed in one equipment using a generated test pattern. The PC test and automatic test are separated using a high speed switching device which is capable of implementing a conversion without a signal distortion between the signal lines extended from the chip sets and the pattern generation substrate. Therefore, in the present invention, it is possible to enhance a test performance and decrease the test time and error ratio and cost of the products.

摘要翻译： 本发明涉及一种芯片存储器件的测试设备。 使用图案生成基板实现记忆图案测试，其中处理器被设计在EPLD中，从而实现PC测试和图案编程，使得在由CPU和芯片组形成的PC环境下评估的测试。 使用生成的测试图案在一个设备中执行芯片器件测试和自动测试的两个过程。 PC测试和自动测试使用能够实现从芯片组和图案生成基板延伸的信号线之间没有信号失真的转换的高速开关器件分离。 因此，在本发明中，能够提高测试性能并降低产品的测试时间和误差率和成本。