公开(公告)号：US07418578B2

公开(公告)日：2008-08-26

申请号：US11273679

申请日：2005-11-14

申请人： Hung Nguyen ,  Shannon Wichman

发明人： Hung Nguyen ,  Shannon Wichman

IPC分类号： G06F9/38

CPC分类号： G06F9/3853 ,  G06F9/30072

摘要： A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple state machines simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes multiple attribute queues simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes write enable logic and an execution unit. The write enable logic produces write enable signals dependent upon received attributes, and the execution unit saves results of instructions of conditional execution instruction groups dependent upon the write enable signals.

摘要翻译： 公开了一种处理器，其包括允许处理器同时执行多个条件执行指令组的指令的若干特征。 每个条件执行指令组包括条件执行指令和由条件执行指令指定的代码块。 在一个实施例中，处理器包括可同时分配给相应数量的条件执行指令组的多个状态机。 在另一实施例中，处理器包括多个寄存器，用于存储与多个执行流水线级中的每一个中的多个指令有关的标记数据。 在另一个实施例中，处理器包括可同时分配给相应数量的条件执行指令组的多个属性队列。 在另一个实施例中，处理器包括写使能逻辑和执行单元。 写使能逻辑根据接收的属性产生写使能信号，执行单元根据写使能信号保存条件执行指令组的指令结果。

公开(公告)号：US07275149B1

公开(公告)日：2007-09-25

申请号：US10396265

申请日：2003-03-25

申请人： Senthil K. Subramanian ,  Hung T. Nguyen

发明人： Senthil K. Subramanian ,  Hung T. Nguyen

IPC分类号： G06F9/00

CPC分类号： G06F9/00

摘要： A system, circuit, and method are presented for evaluating conditional execution instructions. The system, circuit, and method are adapted to receive an identification instruction comprising the size and the condition of execution of a block of conditional execution instructions. The system, circuit, and method may also be coupled to determine a position and for a conditional execution instruction within a block of conditional execution instructions. The system, circuit, and method can determine whether a conditional field, in which the conditional field comprises a type of conditional execution instruction, meets a condition of execution. By determining the size of the block of conditional execution by an identification instruction and determining the type of conditional execution instruction, the system, circuit and method advantageously decreases the code density of a set of instruction, and advantageously increases the overall performance of a processor.

摘要翻译： 提出了一种用于评估条件执行指令的系统，电路和方法。 系统，电路和方法适于接收包括执行条件执行指令块的大小和条件的标识指令。 系统，电路和方法还可以被耦合以确定位置和条件执行指令块内的条件执行指令。 系统，电路和方法可以确定条件字段是否包括条件执行指令的类型的条件字段是否满足执行条件。 通过由识别指令确定条件执行块的大小并确定条件执行指令的类型，系统，电路和方法有利地降低了一组指令的代码密度，并且有利地增加了处理器的整体性能。

公开(公告)号：US07251721B1

公开(公告)日：2007-07-31

申请号：US09993114

申请日：2001-11-05

申请人： Hung T. Nguyen ,  Shannon A. Wichman

发明人： Hung T. Nguyen ,  Shannon A. Wichman

IPC分类号： G06F15/00

CPC分类号： G06F9/3842 ,  G06F9/30058 ,  G06F9/381 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

摘要： For use in a wide-issue processor, a mechanism for, and method of, conditionally executing instructions and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a conditional execution block state machine that tags and generates link pointers for instructions located in a conditional execution block and (2) conditional link pointer registers, associated with stages in a pipeline of the processor, that contain and cause the link pointers to move therethrough as the instructions located in the conditional execution block move through the stages.

摘要翻译： 用于广泛问题的处理器，有条件地执行指令的机制和方法以及结合该机制或方法的数字信号处理器（DSP）。 在一个实施例中，该机制包括：（1）条件执行块状态机，其对位于条件执行块中的指令进行标签和生成链接指针;以及（2）与处理器流水线中的级相关联的条件链接指针寄存器， 它包含并导致链接指针移动通过，因为位于条件执行块中的指令移动通过阶段。

公开(公告)号：US07574468B1

公开(公告)日：2009-08-11

申请号：US11083575

申请日：2005-03-18

申请人： Jitendra Rayala

发明人： Jitendra Rayala

IPC分类号： G06F17/14

CPC分类号： G06F17/147

摘要： A distributed arithmetic multiply/accumulate (MAC) unit for computing inverse discrete cosine transformations (IDCTs). In one embodiment, the distributed arithmetic MAC unit includes: (1) a first pipeline stage configured to perform dot products on received sequential input data and (2) a second pipeline stage coupled to the first pipeline stage and configured to compute additions and subtractions of the dot products to yield sequential output data.

摘要翻译： 用于计算逆离散余弦变换（IDCT）的分布式算术乘法/累积（MAC）单元。 在一个实施例中，分布式算术MAC单元包括：（1）第一流水线级，被配置为在接收到的顺序输入数据上执行点积;以及（2）第二流水线级，其耦合到第一流水线级并且被配置为计算加法和减法 点产品产生顺序输出数据。

公开(公告)号：US07360117B1

公开(公告)日：2008-04-15

申请号：US10279344

申请日：2002-10-24

申请人： Mark A. Boike ,  Alan Phan ,  Brendon J. Slade

发明人： Mark A. Boike ,  Alan Phan ,  Brendon J. Slade

IPC分类号： G06F11/00

CPC分类号： G06F11/3652

摘要： An in-circuit emulation debugger and method of operating an in-circuit emulation debugger to test a digital signal processor (DSP). In one embodiment, the in-circuit emulation debugger includes: (1) a device emulation unit, coupled to a collocated DSP core, for emulating circuitry that is to interact with the DSP core, (2) an external processor interface, coupled to the device emulation unit, that receives control signals from an external processor that cause the device emulation unit to provide a test environment for the DSP core and (3) a breakpoint detection circuit, associated with the device emulation unit, that responds to preprogrammed breakpoints based on occurrences of events both internal and external to the DSP core.

摘要翻译： 一种在线仿真调试器和操作在线仿真调试器来测试数字信号处理器（DSP）的方法。 在一个实施例中，在线仿真调试器包括：（1）耦合到并置的DSP核的器件仿真单元，用于仿真与DSP内核交互的电路;（2）外部处理器接口，耦合到 设备仿真单元，其接收来自外部处理器的控制信号，所述控制信号使得所述设备仿真单元为所述DSP内核提供测试环境;以及（3）与所述设备仿真单元相关联的断点检测电路，所述断点检测电路基于预编程的断点， 事件发生在DSP核心的内部和外部。

公开(公告)号：US07272704B1

公开(公告)日：2007-09-18

申请号：US10844941

申请日：2004-05-13

申请人： Hung Nguyen ,  Shannon Wichman

发明人： Hung Nguyen ,  Shannon Wichman

IPC分类号： G06F9/44

CPC分类号： G06F9/325 ,  G06F9/30058 ,  G06F9/324 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3875 ,  G06F9/3885

摘要： A hardware looping mechanism and method is described herein for handling any number and/or type of discontinuity instruction that may arise when executing program instructions within a scalar or superscalar processor. For example, the hardware looping mechanism may provide zero-overhead looping for branch instructions, in addition to single loop constructs and multiple loop constructs (which may or may not be nested). Zero-overhead looping may also be provided in special cases, e.g., when servicing an interrupt or executing a branch-out-of-loop instruction. In addition to reducing the number of instructions required to execute a program, as well as the overall time and power consumed during program execution, the hardware looping mechanism described herein may be integrated within any processor architecture without modifying existing program code.

摘要翻译： 本文描述了用于处理在标量或超标量处理器中执行程序指令时可能出现的任何数量和/或类型的不连续指令的硬件循环机制和方法。 例如，除了单个循环结构和多个循环结构（其可以嵌套或可以不嵌套）之外，硬件循环机制可以为分支指令提供零开销循环。 在特殊情况下也可以提供零开销循环，例如当服务于中断或执行分支回路指令时。 除了减少执行程序所需的指令数量以及在程序执行期间消耗的总体时间和功耗之外，本文描述的硬件循环机制可以集成在任何处理器架构中而不修改现有的程序代码。

公开(公告)号：US07231510B1

公开(公告)日：2007-06-12

申请号：US10007498

申请日：2001-11-13

申请人： Hung T. Nguyen ,  Shannon A. Wichman

发明人： Hung T. Nguyen ,  Shannon A. Wichman

IPC分类号： G06F7/483

CPC分类号： G06F7/5443 ,  G06F2207/3884

摘要： A mechanism for, and method of, processing multiply-accumulate instructions with out-of-order completion in a pipeline, for use in a processor having an at least four-wide instruction issue architecture, and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism including: (1) a multiply-accumulate unit (MAC) having an initial multiply stage and a subsequent accumulate stage and (2) out-of-order completion logic, associated with the MAC, that causes interim results produced by the multiply stage to be stored when the accumulate stage is unavailable and allows younger instructions to complete before the multiply-accumulate instructions.

摘要翻译： 一种用于处理具有至少四个宽度的指令问题架构的处理器的流水线中的无序完成处理多重累加指令的机制和方法，以及数字信号处理器（DSP） 机制或方法。 在一个实施例中，该机制包括：（1）具有初始乘法级和后续累加级的乘法累积单元（MAC），以及（2）与MAC相关联的无序完成逻辑，其导致中间结果 在累加阶段不可用时由乘法级产生，并允许较少的指令在乘法累加指令之前完成。

公开(公告)号：US20080313433A1

公开(公告)日：2008-12-18

申请号：US12196102

申请日：2008-08-21

申请人： Hung Nguyen ,  Shannon Wichman

发明人： Hung Nguyen ,  Shannon Wichman

IPC分类号： G06F9/38

CPC分类号： G06F9/3853 ,  G06F9/30072

摘要： A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes write enable logic and an execution unit. The write enable logic produces write enable signals dependent upon received attributes, and the execution unit saves results of instructions of conditional execution instruction groups dependent upon the write enable signals.

摘要翻译： 公开了一种处理器，其包括允许处理器同时执行多个条件执行指令组的指令的若干特征。 每个条件执行指令组包括条件执行指令和由条件执行指令指定的代码块。 在一个实施例中，处理器包括多个寄存器，用于存储与多个执行流水线级中的每一个中的多个指令有关的标记数据。 在另一个实施例中，处理器包括写使能逻辑和执行单元。 写使能逻辑根据接收的属性产生写使能信号，执行单元根据写使能信号保存条件执行指令组的指令结果。

公开(公告)号：US07299343B2

公开(公告)日：2007-11-20

申请号：US10256864

申请日：2002-09-27

申请人： Seshagiri P. Kalluri ,  Ramon C. Trombetta ,  Adam C. Krolnik

发明人： Seshagiri P. Kalluri ,  Ramon C. Trombetta ,  Adam C. Krolnik

IPC分类号： G06F9/44

CPC分类号： G06F9/30094 ,  G06F9/30101 ,  G06F9/30181 ,  G06F9/3842

摘要： A system for conditionally executing an instruction depending on a previously existing condition. The system disclosed is configured to handle conditional execution instructions typically specifying at least one target instruction, a processor register, and a condition within the register. The system saves a result of each of the target instructions dependent upon the existence of the condition in the specified register during execution of the conditional execution instruction. When the conditional execution instruction specifies a first flag register, the system copies the flag bits in the first flag register to a corresponding second flag register, and saves a result of each of the target instructions dependent upon the specified condition in the first flag register during execution of the conditional execution instruction. A subsequent conditional execution instruction may then specify a condition in the second flag register in order to conditionally execute target instructions based on a previously existing condition.

摘要翻译： 根据先前存在的条件有条件地执行指令的系统。 所公开的系统被配置为处理通常指定至少一个目标指令，处理器寄存器和寄存器内的条件的条件执行指令。 在执行条件执行指令期间，系统保存每个目标指令的结果，这取决于指定寄存器中条件的存在。 当条件执行指令指定第一标志寄存器时，系统将第一标志寄存器中的标志位复制到对应的第二标志寄存器，并且在第一标志寄存器期间将取决于指定条件的每个目标指令的结果保存在第一标志寄存器中 执行条件执行指令。 随后的条件执行指令可以指定第二标志寄存器中的条件，以便基于先前存在的条件有条件地执行目标指令。