公开(公告)号：US07251721B1

公开(公告)日：2007-07-31

申请号：US09993114

申请日：2001-11-05

申请人： Hung T. Nguyen ,  Shannon A. Wichman

发明人： Hung T. Nguyen ,  Shannon A. Wichman

IPC分类号： G06F15/00

CPC分类号： G06F9/3842 ,  G06F9/30058 ,  G06F9/381 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

摘要： For use in a wide-issue processor, a mechanism for, and method of, conditionally executing instructions and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a conditional execution block state machine that tags and generates link pointers for instructions located in a conditional execution block and (2) conditional link pointer registers, associated with stages in a pipeline of the processor, that contain and cause the link pointers to move therethrough as the instructions located in the conditional execution block move through the stages.

摘要翻译： 用于广泛问题的处理器，有条件地执行指令的机制和方法以及结合该机制或方法的数字信号处理器（DSP）。 在一个实施例中，该机制包括：（1）条件执行块状态机，其对位于条件执行块中的指令进行标签和生成链接指针;以及（2）与处理器流水线中的级相关联的条件链接指针寄存器， 它包含并导致链接指针移动通过，因为位于条件执行块中的指令移动通过阶段。

公开(公告)号：US07231510B1

公开(公告)日：2007-06-12

申请号：US10007498

申请日：2001-11-13

申请人： Hung T. Nguyen ,  Shannon A. Wichman

发明人： Hung T. Nguyen ,  Shannon A. Wichman

IPC分类号： G06F7/483

CPC分类号： G06F7/5443 ,  G06F2207/3884

摘要： A mechanism for, and method of, processing multiply-accumulate instructions with out-of-order completion in a pipeline, for use in a processor having an at least four-wide instruction issue architecture, and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism including: (1) a multiply-accumulate unit (MAC) having an initial multiply stage and a subsequent accumulate stage and (2) out-of-order completion logic, associated with the MAC, that causes interim results produced by the multiply stage to be stored when the accumulate stage is unavailable and allows younger instructions to complete before the multiply-accumulate instructions.

摘要翻译： 一种用于处理具有至少四个宽度的指令问题架构的处理器的流水线中的无序完成处理多重累加指令的机制和方法，以及数字信号处理器（DSP） 机制或方法。 在一个实施例中，该机制包括：（1）具有初始乘法级和后续累加级的乘法累积单元（MAC），以及（2）与MAC相关联的无序完成逻辑，其导致中间结果 在累加阶段不可用时由乘法级产生，并允许较少的指令在乘法累加指令之前完成。

公开(公告)号：US07051146B2

公开(公告)日：2006-05-23

申请号：US10603303

申请日：2003-06-25

申请人： Hung T. Nguyen ,  Shannon A. Wichman

发明人： Hung T. Nguyen ,  Shannon A. Wichman

IPC分类号： G06F13/14

CPC分类号： G06F9/30145 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3824 ,  G06F9/3885

摘要： A processor is disclosed that executes an instruction including a user-defined value (an address or a command) and provides the user-defined value during execution of the instruction. In one embodiment the processor includes a bus interface adapted for coupling to a bus, and the processor drives the user-defined address or command upon one or more signal lines of the bus via the bus interface during execution of the instruction. A described data processing system includes the processor coupled to a device including an addressable register. The device receives a user-defined address from the processor and accesses the addressable register in response to the user-defined address. Methods are disclosed for obtaining a value stored in an addressable register, providing a value stored in an addressable register, storing a value in an addressable register, and modifying a value stored in an addressable register.

摘要翻译： 公开了一种处理器，其执行包括用户定义值（地址或命令）的指令，并在执行指令期间提供用户定义的值。 在一个实施例中，处理器包括适于耦合到总线的总线接口，并且处理器在执行指令期间经由总线接口在总线的一个或多个信号线上驱动用户定义的地址或命令。 所描述的数据处理系统包括耦合到包括可寻址寄存器的设备的处理器。 设备从处理器接收用户定义的地址，并响应于用户定义的地址访问可寻址寄存器。 公开了用于获得存储在可寻址寄存器中的值的方法，提供存储在可寻址寄存器中的值，将值存储在可寻址寄存器中，以及修改存储在可寻址寄存器中的值。

公开(公告)号：US6112273A

公开(公告)日：2000-08-29

申请号：US719599

申请日：1996-09-25

申请人： Weiyuen Kau ,  John H. Cornish ,  Qadeer A. Qureshi ,  Shannon A. Wichman

发明人： Weiyuen Kau ,  John H. Cornish ,  Qadeer A. Qureshi ,  Shannon A. Wichman

IPC分类号： G06F13/24 ,  G06F9/18

CPC分类号： G06F13/24

摘要： An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit (110) has a system management interrupt (SMI#) output pin and SMI circuitry (2370) including a SMI register (2610) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC (110) further has a mask SMI register (2620) connected to the SMI register (2610) to select particular ones of the events sources for SMI response. A logic circuit (2634, 2638) is fed by the SMI register (2610) for combining the selected events sources to supply an internal SMI output (SMIOUT). Other circuits, systems and methods are also disclosed.

摘要翻译： 电子系统（100）包括具有卡系统管理中断（SMI）输出引脚（CRDSMI＃）和中断引脚（IRQ3-5）的第一集成电路（IC）（112）和逻辑电路（1620,1630） 具有连接到卡SMI引脚的输出。 该逻辑电路还具有分别连接到用于第一和第二卡（CARD A，B）的第一和第二组寄存器和逻辑的输入。 第一和第二组寄存器和逻辑中的每一个包括分别由至少卡事件（CDCHG）和电池条件事件（BWARN）设置位的第一寄存器（CSC REG）。 逻辑门（2672）响应于组合来自第一寄存器的位。 第二个寄存器（INT AND GEN CTRL REG）具有一个位（SMIEN），用于根据位的状态（SMIEN）指导逻辑门（2672）的输出用于普通中断或用于系统管理中断。 第二集成电路（110）具有系统管理中断（SMI＃）输出引脚和SMI电路（2370），其包括连接到包括第一集成电路的卡SMI输出的符合SMI响应的事件源的SMI寄存器（2610）。 该第二IC（110）还具有连接到SMI寄存器（2610）的掩模SMI寄存器（2620），以选择SMI响应的特定事件源。 逻辑电路（2634,2638）由SMI寄存器（2610）馈送，用于组合所选择的事件源以提供内部SMI输出（SMIOUT）。 还公开了其它电路，系统和方法。

公开(公告)号：US07079147B2

公开(公告)日：2006-07-18

申请号：US10437485

申请日：2003-05-14

申请人： Shannon A. Wichman ,  Ramon C. Trombetta ,  Yetung P. Chiang

发明人： Shannon A. Wichman ,  Ramon C. Trombetta ,  Yetung P. Chiang

IPC分类号： G06F15/16 ,  G06F13/14 ,  G06F15/76 ,  G06F9/40 ,  G06T1/00 ,  G06K9/46

CPC分类号： H04N19/43 ,  H04N5/145 ,  H04N19/523

摘要： A disclosed coprocessor receives a user-defined command during execution of an instruction including the user-defined command, and performs a predetermined function in response to the user-defined command. The user-defined command includes multiple ordered bits having values assigned by a user. In one embodiment, the coprocessor includes logic coupled to receive the user-defined command and a datapath. The logic produces a control value in response to the user-defined command. The datapath receives data and the control value, and performs the predetermined function dependent upon the control value. In one embodiment, the predetermined function is a motion estimation function. Data processing systems are described including a processor coupled to the coprocessor. Another disclosed data processing system includes an arbiter coupled between a processor and multiple coprocessors. The arbiter receives the user-defined command, and provides the user-defined command to one of the coprocessors dependent upon the user-defined command.

摘要翻译： 所公开的协处理器在执行包括用户定义的命令的指令期间接收用户定义的命令，并且响应于用户定义的命令执行预定的功能。 用户定义的命令包括具有由用户分配的值的多个有序位。 在一个实施例中，协处理器包括耦合以接收用户定义的命令和数据路径的逻辑。 该逻辑产生响应于用户定义的命令的控制值。 数据通路接收数据和控制值，并根据控制值执行预定功能。 在一个实施例中，预定功能是运动估计功能。 描述了数据处理系统，包括耦合到协处理器的处理器。 另一公开的数据处理系统包括耦合在处理器和多个协处理器之间的仲裁器。 仲裁器接收用户定义的命令，并根据用户定义的命令将用户定义的命令提供给协处理器之一。

公开(公告)号：US06745314B1

公开(公告)日：2004-06-01

申请号：US09994459

申请日：2001-11-26

申请人： Shannon A. Wichman

发明人： Shannon A. Wichman

IPC分类号： G06F1200

CPC分类号： G06F5/10 ,  G06F2205/106

摘要： A circular buffer control circuit, a method of controlling a circular buffer and a digital signal processor (DSP) incorporating the circuit or the method. In one embodiment, the circuit includes: (1) address calculation logic, having multiple datapaths, that calculates, from data regarding a buffer operation, an updated address result therefor and (2) modification order determination circuitry, coupled in parallel with the address calculation logic, that transmits a memory access request and the updated address result in an order that is based on whether the buffer operation is pre-modified or post-modified.

摘要翻译： 一种循环缓冲器控制电路，一种控制循环缓冲器的方法和一种结合电路或方法的数字信号处理器（DSP）。 在一个实施例中，电路包括：（1）具有多个数据通路的地址计算逻辑，其从关于缓冲器操作的数据计算其更新的地址结果，以及（2）与地址计算并行地耦合的修改顺序确定电路 逻辑，其传送存储器访问请求，并且更新的地址结果是基于缓冲区操作是预先修改还是后修改的顺序。

公开(公告)号：US06421754B1

公开(公告)日：2002-07-16

申请号：US08480179

申请日：1995-06-07

申请人： Weiyuen Kau ,  John H. Cornish ,  Qadeer A. Qureshi ,  Shannon A. Wichman

发明人： Weiyuen Kau ,  John H. Cornish ,  Qadeer A. Qureshi ,  Shannon A. Wichman

IPC分类号： G06F1324

CPC分类号： G06F13/24

摘要： An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit (110) has a system management interrupt (SMI#) output pin and SMI circuitry (2370) including a SMI register (2610) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC (110) further has a mask SMI register (2620) connected to the SMI register (2610) to select particular ones of the events sources for SMI response. A logic circuit (2634, 2638) is fed by the SMI register (2610) for combining the selected events sources to supply an internal SMI output (SMIOUT). Other circuits, systems and methods are also disclosed.

摘要翻译： 电子系统（100）包括具有卡系统管理中断（SMI）输出引脚（CRDSMI＃）和中断引脚（IRQ3-5）的第一集成电路（IC）（112）和逻辑电路（1620,1630） 具有连接到卡SMI引脚的输出。 该逻辑电路还具有分别连接到用于第一和第二卡（CARD A，B）的第一和第二组寄存器和逻辑的输入。 第一和第二组寄存器和逻辑中的每一个包括分别由至少卡事件（CDCHG）和电池条件事件（BWARN）设置位的第一寄存器（CSC REG）。 逻辑门（2672）响应于组合来自第一寄存器的位。 第二个寄存器（INT AND GEN CTRL REG）具有一个位（SMIEN），用于根据位的状态（SMIEN）指导逻辑门（2672）的输出用于普通中断或用于系统管理中断。 第二集成电路（110）具有系统管理中断（SMI＃）输出引脚和SMI电路（2370），其包括连接到包括第一集成电路的卡SMI输出的符合SMI响应的事件源的SMI寄存器（2610）。 该第二IC（110）还具有连接到SMI寄存器（2610）的掩模SMI寄存器（2620），以选择SMI响应的特定事件源。 逻辑电路（2634,2638）由SMI寄存器（2610）馈送，用于组合所选择的事件源以提供内部SMI输出（SMIOUT）。 还公开了其它电路，系统和方法。

公开(公告)号：US5712991A

公开(公告)日：1998-01-27

申请号：US374357

申请日：1995-01-18

申请人： Shannon A. Wichman ,  John Cornish ,  Qadeer A. Qureshi

发明人： Shannon A. Wichman ,  John Cornish ,  Qadeer A. Qureshi

IPC分类号： G06F3/06 ,  G06F13/40 ,  G06F13/14

CPC分类号： G06F3/061 ,  G06F13/4059 ,  G06F3/0656 ,  G06F3/0674

摘要： A peripheral controller device (14) controlling at least a first peripheral device (16) attached thereto, the controller device including a programmable and selectable buffer memory for utilization with a first type and a second type of write instruction for writing data to first type (24) and a second type (26), respectively, of memory in the peripheral device (16). The peripheral controller device includes an n deep buffer memory (36), where n is an integer greater than one, for buffering the write instructions. A user may programmably indicate whether only the first type of write instruction is to be buffered or both types of instructions are to be buffered. Responsive to such programming, write instructions are examined to determine if they are of the first type or the second type. Depending on the programming, write instructions of the second type are routed to the buffer or are routed by bypassing the buffer memory.

摘要翻译： 控制至少第一外围设备（16）附连到其上的外围控制器设备（14），所述控制器设备包括用于将数据写入第一类型的第一类型和第二类型写入指令的可编程和可选择的缓冲存储器 24）和外围设备（16）中的存储器的第二类型（26）。 外围控制器装置包括n个深缓冲存储器（36），其中n是大于1的整数，用于缓冲写入指令。 用户可以可编程地指示是否要缓冲第一类写入指令或者两种类型的指令都被缓冲。 响应于这种编程，检查写入指令以确定它们是第一类型还是第二类型。 根据编程，第二种类型的写入指令被路由到缓冲区，或通过绕过缓冲存储器进行路由。

公开(公告)号：US5630108A

公开(公告)日：1997-05-13

申请号：US375317

申请日：1995-01-18

申请人： Shannon A. Wichman ,  John Cornish ,  Qadeer A. Qureshi

发明人： Shannon A. Wichman ,  John Cornish ,  Qadeer A. Qureshi

IPC分类号： G06F13/42 ,  G06F1/10

CPC分类号： G06F13/4217

摘要： A bus interface timing unit responsive to a system clock signal having a frequency that is selectable among a plurality of frequencies. The bus interface timing unit provides timing signals to a bus interface unit that performs functions involving control signals having predetermined timing requirements, such timing requirements being substantially independent of the frequency of the system clock signal. The bus interface timing unit includes a signal generator (20) which is responsive to the system clock signal, and which generates the control signals. These control signals include at least one event signal controlling a time duration in which a predetermined event occurs. Also included is a control unit (10), responsive to a signal representative of the selected frequency of the system clock signal, that controls the signal generator such that the event signal timing is generated in accordance with the predetermined requirements the selected frequencies.

摘要翻译： 总线接口定时单元，其响应于具有可在多个频率中选择的频率的系统时钟信号。 总线接口定时单元向总线接口单元提供定时信号，总线接口单元执行涉及具有预定定时要求的控制信号的功能，这种定时要求基本上与系统时钟信号的频率无关。 总线接口定时单元包括响应于系统时钟信号并产生控制信号的信号发生器（20）。 这些控制信号包括控制发生预定事件的持续时间的至少一个事件信号。 还包括控制单元（10），其响应于表示系统时钟信号的选定频率的信号，其控制信号发生器，使得根据所选频率的预定要求生成事件信号定时。

公开(公告)号：US07171609B2

公开(公告)日：2007-01-30

申请号：US10613128

申请日：2003-07-03

申请人： Danny W. Wilson ,  Shannon A. Wichman

发明人： Danny W. Wilson ,  Shannon A. Wichman

IPC分类号： H03M13/03

CPC分类号： H03M13/6502 ,  H03M13/23 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6569

摘要： A disclosed processor includes update logic coupled to a register. The update logic receives a first signal indicative of a first add-compare-select (ACS) instruction result and a second signal indicative of a second ACS instruction result, and updates the contents of the register dependent upon the first and second signals. In the event the first and second signals are received substantially simultaneously, the update logic shifts the contents of the register 2 bit positions in order thereby vacating 2 consecutive bit positions, updates one of the vacated bit positions dependent upon the first signal, and updates the other vacated bit position dependent upon the second signal. A described method for decoding convolutional code includes generating computer program code for a processor including two or more ACS instructions. Storage elements specified by each of the ACS instructions are selected such that the processor can execute the ACS instructions substantially simultaneously.

摘要翻译： 所公开的处理器包括耦合到寄存器的更新逻辑。 更新逻辑接收指示第一加法比较选择（ACS）指令结果的第一信号和指示第二ACS指令结果的第二信号，并根据第一和第二信号更新寄存器的内容。 在基本上同时接收到第一和第二信号的情况下，更新逻辑将寄存器2位位置的内容移位，从而使2个连续的位位置空出，根据第一信号更新一个空出位位置，并更新 取决于第二信号的其它空位位置。 所描述的用于解码卷积码的方法包括为包括两个或多个ACS指令的处理器生成计算机程序代码。 选择由每个ACS指令指定的存储元件，使得处理器可以基本上同时执行ACS指令。