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公开(公告)号：US20240347584A1
公开(公告)日：2024-10-17
申请号：US18340485
申请日：2023-06-23
发明人： Tetsuya OKADA , Kikuo OKADA , Hiroki ARAI
IPC分类号： H01L29/06 , H01L29/10 , H01L29/861
CPC分类号： H01L29/0603 , H01L29/1095 , H01L29/861
摘要： [Problem to be solved] To reduce recovery loss.
[Solution] A semiconductor device 10 includes: an anode electrode 20, formed on a front surface of a semiconductor substrate 12; a cathode electrode 22, formed on a back surface; a P layer 16, formed on the anode electrode 20 side; an N layer 14, formed on the cathode electrode 22 side; an N+ layer 26, arranged between the P layer 16 and the N layer 14 and having a higher carrier concentration than the N layer 14; and an anode trench 30, which extends from the front surface of the semiconductor substrate 12 toward the back surface side thereof and extends to the N+ layer 26 through the P layer 16, and in which an insulating film 32 is formed between the peripheral N+ layer 26, and a conductive material 34 arranged inside is connected to the anode electrode 20.-
2.发明公开公开(公告)号：US20240274683A1
公开(公告)日：2024-08-15
申请号：US18570253
申请日：2021-12-15
发明人： Shuangshen LE , Zengyi HE , Libo ZHANG , Xingmin WU , Qingwen YUAN
IPC分类号： H01L29/423 , H01L21/28 , H01L29/40
CPC分类号： H01L29/4236 , H01L21/28035 , H01L29/401
摘要： A method for preparing a shielded gate semiconductor device structure, and a shielded gate semiconductor device structure. The following steps are added in between source polycrystalline silicon deposition and gate polycrystalline silicon oxidation: removing, by etching, a first oxide layer and a second oxide layer that are in a middle upper space of a cell trench and on the surface of a semiconductor material layer, and a portion of the semiconductor material layer between trenches; removing, by etching, the gate polycrystalline silicon until a thickness of remaining gate polycrystalline silicon in the source lead-out region trench reaches a preset thickness; and selectively removing, by etching, remaining gate polycrystalline silicon in the source lead-out region trench until no gate polycrystalline silicon remains in the source lead-out region trench, and then removing the photoresist.
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公开(公告)号：US20240204732A1
公开(公告)日：2024-06-20
申请号：US18158155
申请日：2023-01-23
发明人： HIROYUKI KIMURA
CPC分类号： H03F1/08 , H03F3/45179 , H03F2200/372
摘要： An amplifier circuit includes a first transistor, through which a first input current is made to flow between the drain and the source; a second transistor, through which a second input current is made to flow between the drain and the source; a first-1 current source, which supplies a predetermined current to the gate of the first transistor; a first-2 current source, which supplies a predetermined current to the gate of the second transistor; a pair of adjustable resistors, which are connected in series between the gate of the first transistor and the gate of the second transistor; a connecting path, which connects a connection point of the pair of adjustable resistors to the drain of the first transistor; and a second current source, which supplies a current to the drain of the second transistor.
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公开(公告)号：US20230079309A1
公开(公告)日：2023-03-16
申请号：US17667641
申请日：2022-02-09
IPC分类号： H01L29/423 , H01L29/66 , H01L29/78
摘要： A problem to be solved is to reduce a leakage current between the gate and the source. Provided is a trench type FET, where a thickness Δ1 of an oxide insulating layer O1 that is closer to the inner side than a line extending upward from the outer peripheral side of a nitride insulating layer N is ½ of a thickness d of the nitride insulating layer N or more; and a thickness Δ2 of an oxide insulating layer O3 between the upper end of the nitride insulating layer N and a gate region is ½ of the thickness d of the nitride insulating layer N or more.
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公开(公告)号：US10664676B2
公开(公告)日：2020-05-26
申请号：US15990353
申请日：2018-05-25
IPC分类号： G06K9/00 , G02F1/137 , G02B5/30 , H01L27/32 , G01J1/04 , G02F1/1333 , H01L51/52 , G06T7/73 , G02F1/133 , G06K9/20 , G06K9/42 , G06K9/46 , G06T3/40 , H01L25/16 , G02F1/1368
摘要： An optical sensor system includes a display substrate, display pixel circuitry including a plurality of light emitting display elements or pixels disposed over the display substrate, a first circular polarizer disposed over the display substrate and the display pixel circuitry, and a transparent cover sheet disposed over the first circular polarizer. A top surface of the transparent cover sheet provides a sensing surface for an object such as a finger. The optical sensor system also includes a sensor layer disposed below the display substrate, the sensor layer having a plurality of photosensors, and a second circular polarizer disposed between the sensor layer and the display substrate.
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公开(公告)号：US20240201724A1
公开(公告)日：2024-06-20
申请号：US18155490
申请日：2023-01-17
发明人： HIROYUKI KIMURA
摘要： The disclosure: a positive mirror FET, through which a positive mirror current that is proportional to a positive-direction current in currents of an output FET in positive and negative directions is made to flow; a first operational amplifier, receiving a constant voltage at one end, receiving an upstream side voltage regarding the positive mirror current of the positive mirror FET at the other end, and outputting a voltage corresponding to the upstream side voltage regarding the positive mirror current of the positive mirror FET by converting an output voltage into a current and feeding back the current to the other end; a negative mirror FET, through which a negative mirror current that is proportional to a negative-direction current in the currents of the output FET in positive and negative directions is made to flow; and a second operational amplifier, receiving a constant voltage at one end, receiving an upstream side voltage regarding the negative mirror current of the negative mirror FET at the other end, and outputting a voltage corresponding to the upstream side voltage regarding the negative mirror current of the negative mirror FET by converting an output voltage into a current and feeding back the current to the other end. A detection value is output based on an output current obtained by adding a positive output current corresponding to the output of the first operational amplifier and a negative output current corresponding to the output of the second operational amplifier.
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公开(公告)号：US20230396148A1
公开(公告)日：2023-12-07
申请号：US17858304
申请日：2022-07-06
发明人： Hiroyuki KIMURA
CPC分类号： H02M1/083 , H02M1/0009 , H02M3/155
摘要： A switch circuit includes: a p-channel pass transistor, in which the source is connected to a power source and the drain is connected to a load; and a gate drive circuit, which is connected to the gate of the pass transistor. The gate drive circuit includes: a first transistor, through which a first current is made to flow by turn-on of an on/off signal; and an amplifier, in which a reference voltage corresponding to the first current is input to the negative input end, and a gate voltage of the gate is input to the positive input end, and which controls a gate current from the gate by an output from the output end in a manner that the gate voltage matches the reference voltage, and is capable of setting a maximum current of the output. A soft-on time from turn-on of the on/off signal to turn-on of the pass transistor is set by setting the maximum current according to the gate capacitance of the pass transistor.
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公开(公告)号：US11669125B1
公开(公告)日：2023-06-06
申请号：US17833995
申请日：2022-06-07
发明人： Hiroyuki Kimura
CPC分类号： G06F1/08 , G06F1/10 , H03K5/00006 , H03K19/20
摘要： The clock generation circuit outputs a clock signal with a constant cycle by repeating the following operations: when an enable signal becomes a H level, the clock signal immediately rises, and a sense end is changed to a L level via a first capacitor, then a voltage of the sense end is gradually increased via a resistor, and when the sense end reaches a predetermined potential, an output of a second inverter becomes the L level, the clock signal becomes the L level, an inverted clock signal becomes the H level, and accordingly the sense end becomes the H level; and thereafter, a current flows via the resistor so that the voltage of the sense end decreases gradually, when the sense end reaches a predetermined potential, the output of the second inverter becomes a H level, the clock signal becomes the H level, the sense end is changed to a L level via the first capacitor, then the voltage of the sense end is gradually increased via the resistor, and when the sense end reaches a predetermined potential, the output of the second inverter becomes the L level and the clock signal becomes the L level.
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公开(公告)号：US20200278482A1
公开(公告)日：2020-09-03
申请号：US16878138
申请日：2020-05-19
发明人： Patrick Smith , Paul Wickboldt , Patrick A. Worfolk , Steven Molesa , Young Lee , Richard Klenkler
摘要： Fingerprint sensors include a plurality of optical sensor elements, a collimator filter disposed above the plurality of optical sensor elements, and a display disposed above the collimator filter, wherein the display is a fingerprint imaging light source. The collimator filter has a plurality of apertures, and the plurality of optical sensor elements is configured to receive light transmitted through one aperture of the plurality of apertures.
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公开(公告)号：US20240356542A1
公开(公告)日：2024-10-24
申请号：US18213567
申请日：2023-06-23
发明人： Tetsuya OKADA , Hiroki ARAI
IPC分类号： H03K17/16 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/739
CPC分类号： H03K17/168 , H01L29/1095 , H01L29/407 , H01L29/41708 , H01L29/7397
摘要： [Problem to be solved] To reduce a loss according to an operating condition of high-frequency use or low-frequency use.
[Solution] A trench gate type IGBT includes: a gate trench 120G, which extends from the front surface toward the back surface side of a semiconductor substrate, and causes a current to flow through a channel region formed in the periphery by an applied voltage; a switch trench 120SW, which extends from the front surface toward the back surface side of the semiconductor substrate and has no channel region formed therearound; and a setting terminal for externally controlling the voltage of the switch trench 120SW. A switching between a first state, in which a voltage drop at on-time is relatively small and an energy loss at turn-off time is relatively large, and a second state, in which the voltage drop at on-time is relatively large and the energy loss at turn-off time is relatively small, can be performed, according to a voltage applied to the setting terminal.
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