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    Integrated quantum computer incorporating quantum core and associated classical control circuitry
    1.
    发明授权
    Integrated quantum computer incorporating quantum core and associated classical control circuitry 有权

    公开(公告)号：US11423322B2

    公开(公告)日：2022-08-23

    申请号：US16734346

    申请日：2020-01-05

    申请人： equal1.labs Inc.

    发明人： Dirk Robert Walter Leipold ,  George Adrian Maxim ,  Michael Albert Asker

    IPC分类号： G06N10/00 ,  G06F1/20 ,  G06F15/78 ,  G06F15/16

    摘要： A novel and useful fully integrated quantum computer containing both quantum core circuitry and associated classical electronic control circuits on the same monolithic die. The integrated quantum computer avoids ESD loading on the quantum structures and minimizes the need for long interconnects with resultant large parasitic inductances and capacitances. Such parasitics reduce the maximum operating frequency of the realized quantum core structures. A cryostat unit functions to provide several temperatures to the quantum computer including a temperature to cool the quantum core to approximately 4° K and the interface SoC to 77° K. Alternatively, the interface circuitry is also integrated with the main QPU on the same die. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations.

    SYSTEM AND METHOD OF GENERATING QUANTUM UNITARY NOISE USING SILICON BASED QUANTUM DOT ARRAYS
    2.
    发明申请
    SYSTEM AND METHOD OF GENERATING QUANTUM UNITARY NOISE USING SILICON BASED QUANTUM DOT ARRAYS 有权

    公开(公告)号：US20220149823A1

    公开(公告)日：2022-05-12

    申请号：US17522835

    申请日：2021-11-09

    申请人： equal1.labs Inc.

    发明人： David J. REDMOND ,  Dirk Robert Walter LEIPOLD ,  Imran BASHIR ,  Robert Bogdan STASZEWSKI

    IPC分类号： H03K3/84 ,  H01L29/66 ,  G06N10/00 ,  G06N3/04 ,  G06N3/08

    摘要： A novel and useful system and method of generating quantum unitary noise using silicon based quantum dot arrays. Unitary noise is derived from a probability of detecting a particle within a quantum dot array structure comprising position based charge qubits with two time independent basis states |0> and |1>. A two level electron tunneling device such as an interface device, qubit or other quantum structure is used to generate quantum noise. The electron tunneling device includes a reservoir of particles, a quantum dot, and a barrier that is used to control tunneling between the reservoir and the quantum dot. A detector circuit connected to the device outputs a digital stream corresponding to the probability of a particle of being detected. Controlling the bias applied to the barrier controls the probability of detection. Thus, the probability density function (PDF) of the output unitary noise can be controlled to correspond to a desired probability. The unitary noise can be used in stochastic rounding by controlling the bias applied to the barrier in accordance with a remainder of numbers to be rounded.

    Semiconductor process for quantum structures with staircase active well
    7.
    发明授权
    Semiconductor process for quantum structures with staircase active well 有权

    公开(公告)号：US10854738B2

    公开(公告)日：2020-12-01

    申请号：US16740521

    申请日：2020-01-13

    申请人： equal1.labs Inc.

    发明人： Dirk Robert Walter Leipold ,  George Adrian Maxim ,  Michael Albert Asker

    IPC分类号： H01L29/66 ,  G06N10/00 ,  H01L29/788 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/15 ,  B82Y10/00 ,  B82Y40/00

    摘要： A novel and useful modified semiconductor process having staircase active well shapes that provide variable distances between pairs of locations (i.e. quantum dots) resulting in modulation of the quantum interaction strength from weak/negligible at large separations to moderate and then strong at short separations. To achieve a modulation of the distance between pairs of locations, diagonal, lateral, and vertical quantum particle/state transport is employed. As examples, both implementations of semiconductor quantum structures with tunneling through an oxide layer and with tunneling through a local well depleted region are disclosed. These techniques are applicable to both planar semiconductor processes and 3D (e.g. Fin-FET) semiconductor processes. Optical proximity correction is used to accommodate the staircase well layers. Each gate control circuit in the imposer circuitry functions to control more than one set of control gates. Thus, each gate control circuit is shared across several qubits which are located sufficiently far from each other to prevent interference. This substantially reduces the number of control signals and control logic that required in the structure.

    QUANTUM SHIFT REGISTER INCORPORATING BIFURCATION
    9.
    发明申请
    QUANTUM SHIFT REGISTER INCORPORATING BIFURCATION 审中-公开

    公开(公告)号：US20190392913A1

    公开(公告)日：2019-12-26

    申请号：US16446325

    申请日：2019-06-19

    申请人： equal1.labs Inc.

    发明人： Dirk Robert Walter Leipold ,  George Adrian Maxim ,  Michael Albert Asker

    IPC分类号： G11C19/12 ,  G06N99/00 ,  G02F1/017

    摘要： A novel and useful controlled quantum shift register for transporting particles from one quantum dot to another in a quantum structure. The shift register incorporates a succession of qdots with tunneling paths and control gates. Applying appropriate control signals to the control gates, a particle or a split quantum state is made to travel along the shift register. The shift register also includes ancillary double interaction where two pairs of quantum dots provide an ancillary function where the quantum state of one pair is replicated in the second pair. The shift register also provides bifurcation where an access path is split into two or more paths. Depending on the control pulse signals applied, quantum dots are extended into multiple paths. Control of the shift register is provided by electric control pulses. An optional auxiliary magnetic field provides additional control of the shift register.

    REPROGRAMMABLE QUANTUM PROCESSOR ARCHITECTURE INCORPORATING CALIBRATION LOOPS
    10.
    发明申请
    REPROGRAMMABLE QUANTUM PROCESSOR ARCHITECTURE INCORPORATING CALIBRATION LOOPS 审中-公开

    公开(公告)号：US20190392342A1

    公开(公告)日：2019-12-26

    申请号：US16446262

    申请日：2019-06-19

    申请人： equal1.labs Inc.

    发明人： Dirk Robert Walter Leipold ,  George Adrian Maxim ,  Michael Albert Asker

    IPC分类号： G06N10/00 ,  G06F15/16

    摘要： A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.