公开(公告)号：US11177984B1

公开(公告)日：2021-11-16

申请号：US16889573

申请日：2020-06-01

Applicant: Xilinx, Inc.

Inventor： Kevin Zheng ,  Chuen-Huei Chou ,  Hsung Jai Im

IPC: H03H7/40 ,  H04L25/03 ,  H04L27/01 ,  H01L21/8238

Abstract: A continuous time linear equalizer (CTLE) is disclosed. The CTLE may include a first cell configured to buffer and invert an input signal and generate a first intermediate signal, a second cell configured to buffer and invert the input signal and generate a second intermediate signal, and a first frequency section configured to selectively buffer and invert a first range of frequencies of the second intermediate signal. The first frequency section may include a first tunable resistor configured to provide a first resistance and a third cell coupled to the first tunable resistor configured to generate a third intermediate signal based on the first resistance.

公开(公告)号：US12160256B2

公开(公告)日：2024-12-03

申请号：US17559592

申请日：2021-12-22

Applicant: XILINX, INC.

Inventor： Chi Fung Poon ,  Chuen-Huei Chou ,  Weerachai Neeranartvong ,  Kevin Zheng

IPC: H04B1/04 ,  H03M1/66 ,  H03M1/74

Abstract: A DAC-based transmit driver architecture with improved bandwidth and techniques for driving data using such an architecture. One example transmit driver circuit generally includes an output node and a plurality of digital-to-analog converter (DAC) slices. Each DAC slice has an output coupled to the output node of the transmit driver circuit and includes a bias transistor having a drain coupled to the output of the DAC slice and a multiplexer having a plurality of inputs and an output coupled to a source of the bias transistor.

公开(公告)号：US11133963B1

公开(公告)日：2021-09-28

申请号：US17011595

申请日：2020-09-03

Applicant: Xilinx, Inc.

Inventor： Kevin Zheng ,  Ronan Casey

IPC: H04L25/03 ,  H03M1/12 ,  H04B1/12

Abstract: Apparatus and associated methods relate to targeted digital correction of a predetermined component of inter-symbol interference (ISI) associated with two or more ranks of cascaded track-and-hold (T/H) front-end circuits of a Time-Interleaved analog-to-digital converter (TI-ADC). In an illustrative example, for two T/H circuit ranks of size N and M, the predetermined component to be compensated may be located at (N×M)th unit interval (UI). A feed forward equalizer (FFE) and/or a decision feedback equalizer (DFE) in a digital signal processing system (DSP) may be then configured to have extra taps and corresponding expanded equalization ranges to mitigate the ISI. Thus, a deterministic ISI component at the N×Mth UI may be digitally corrected by providing equalization with N×M taps at low cost to facilitate scaling to higher bit rates.

公开(公告)号：US11984817B2

公开(公告)日：2024-05-14

申请号：US16814626

申请日：2020-03-10

Applicant: XILINX, INC.

Inventor： Junho Cho ,  Kevin Zheng ,  Parag Upadhyaya

IPC: H02M7/483

CPC classification number: H02M7/483 ,  H02M7/4835

Abstract: An example continuous time linear equalizer (CTLE) includes a first inverter; a second inverter having an input to receive an input signal; a capacitor coupled between an input of the first inverter and the input of the second inverter; a resistor coupled between a common-mode voltage and the input of the first inverter; a third inverter having an output to provide an output signal; and a node comprising an output of the first inverter, an output of the second inverter, an input of the third inverter, and the output of the third inverter.

公开(公告)号：US10998307B1

公开(公告)日：2021-05-04

申请号：US16889533

申请日：2020-06-01

Applicant: Xilinx, Inc.

Inventor： Kevin Zheng ,  Chuen-Huei Chou ,  Hsung Jai Im

IPC: H03M1/00 ,  H01L27/02 ,  H01L27/092 ,  H03M1/66 ,  H03G3/00

Abstract: An analog signal buffer is disclosed. The analog signal buffer may include a transconductance cell and an active load. The active load may load the current from the transconductance cell with a PMOS transistor and an NMOS transistor and provide a feedback resistance. A transimpedance amplifier is disclosed. The transimpedance amplifier may include a first cell configured to receive a first signal and output a second signal and a second cell coupled to the first cell. The second cell may include an active feedback structure configured to couple an output of the second cell to an input of the second cell.

公开(公告)号：US11894959B2

公开(公告)日：2024-02-06

申请号：US17873002

申请日：2022-07-25

Applicant: XILINX, INC.

Inventor： Ronan Sean Casey ,  Lokesh Rajendran ,  Declan Carey ,  Kevin Zheng ,  Catherine Hearne ,  Hongtao Zhang

IPC: H04L25/49 ,  H04L27/04

CPC classification number: H04L25/4917 ,  H04L27/04

Abstract: Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

公开(公告)号：US11522735B1

公开(公告)日：2022-12-06

申请号：US16998864

申请日：2020-08-20

Applicant: Xilinx, Inc.

Inventor： Kevin Zheng ,  Hongtao Zhang ,  Geoffrey Zhang

IPC: H04L25/03 ,  H03H21/00

Abstract: Apparatus and associated methods relate to an ADC-based digital receiver including a feedforward equalizer (FFE) that has m precursor taps and n postcursor taps to equalize the precursor portion, and to adapt postcursor intersymbol interference (ISI) through a predetermined equalization coefficient selected to counteract the noise boosting effect associated with the precursor equalization. In an illustrative example, the receiver may dynamically balance noise and ISI through adaptively determining a coefficient hp1 of a first postcursor tap of a first FFE and a coefficient h1 of a first postcursor tap of a second equalizer adapted to substantially reduce or eliminate additional ISI introduced by the first FFE. The first FFE may optimize ISI removal and noise reduction, for example. One of the coefficients h1 and hp1 may be predetermined, and then the other coefficient may be iteratively adapted to trade off precursor ISI and postcursor ISI to minimize BER.

公开(公告)号：US11489705B1

公开(公告)日：2022-11-01

申请号：US17019035

申请日：2020-09-11

Applicant: XILINX, INC.

Inventor： Ronan Sean Casey ,  Kevin Zheng ,  Catherine Hearne

IPC: H04L25/03 ,  H04L25/02 ,  H04L27/01

Abstract: Some examples described herein provide for an integrated circuit including a continuous time linear equalizer (CTLE) circuit and a method of operating the integrated circuit. In an example, an integrated circuit includes a transconductance amplifier stage and a transimpedance amplifier stage. The transconductance amplifier stage has a first input node and a first output node. The transconductance amplifier stage includes a first complementary device inverter. The transimpedance amplifier stage has a second input node and a second output node. The first output node is electrically connected to the second input node. The transimpedance amplifier stage includes a second complementary device inverter.

公开(公告)号：US11190199B1

公开(公告)日：2021-11-30

申请号：US17103652

申请日：2020-11-24

Applicant: XILINX, INC.

Inventor： Kevin Zheng ,  David Freitas ,  Hsung Jai Im

IPC: H03M1/06 ,  H03M1/46 ,  H03M1/38

Abstract: Examples herein relate to electronic devices that include an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that implements timing adjustment based on output statistics. In an example, an electronic device includes an asynchronous SAR ADC, a statistics monitor, and an operation setting circuit. The asynchronous SAR ADC is configured to output output data. The statistics monitor is configured to capture samples at a bit position of the output data. The statistics monitor is further configured to generate an operational setting based on the captured samples. The operation setting circuit is configured to adjust an operating condition of the asynchronous SAR ADC based on the operational setting.

公开(公告)号：US11764797B2

公开(公告)日：2023-09-19

申请号：US17449293

申请日：2021-09-29

Applicant: XILINX, INC.

Inventor： Kai-An Hsieh ,  Tan Kee Hian ,  Kevin Zheng

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/0607 ,  H03M1/00 ,  H03M1/06 ,  H03M1/10 ,  H03M1/12

Abstract: Analog-to-digital converter circuitry includes comparator circuitry, capacitor analog-to-digital converter circuitry (CDA), and successive approximation register (SAR) circuitry. The comparator circuitry includes a non-inverting input and an inverting input to selectively receive a differential voltage signal, and an output. The CDAC circuitry includes a first capacitor network having a first plurality of capacitors. A first capacitor of the first plurality of capacitors includes a first terminal connected to the non-inverting input and a second terminal selectively connected to a first voltage potential and a second voltage potential. The first voltage potential is greater than the second voltage potential. The SAR circuitry is connected to the output and the first capacitor network, and connects, during a first period, the second terminal of the first capacitor to the second voltage potential. The non-inverting input and the inverting input are connected to the differential voltage signal during the first period.