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    Modular container transport systems
    3.
    发明授权
    Modular container transport systems 有权

    公开(公告)号：US12234033B2

    公开(公告)日：2025-02-25

    申请号：US18242485

    申请日：2023-09-05

    Applicant: Biosphere Aerospace, LLC

    Inventor： Elie Helou, Jr.

    IPC: B64D9/00 ,  B64C1/06 ,  B64C1/22 ,  B65D88/02 ,  B65D88/14 ,  B65D90/00 ,  B65D90/08

    Abstract: A cargo transport system comprising a spine assembly and a container assembly. The spine assembly comprises a rigid spine and a plurality of mounts arranged on the rigid spine in a plurality of mount rows. The container assembly comprises a plurality of containers and is secured to the spine assembly using at least a subset of the plurality of mounts. Each container of the plurality of containers comprises a plurality of fittings for securing the container to the spine assembly and/or another container of the container assembly. Each mount row extends along a width of the spine assembly, and the plurality of mount rows are spaced apart at regular distance intervals along a length of the spine.

    Dual-precision analog memory cell and array
    4.
    发明授权
    Dual-precision analog memory cell and array 有权

    公开(公告)号：US12230309B2

    公开(公告)日：2025-02-18

    申请号：US18528311

    申请日：2023-12-04

    Applicant: HEFEI RELIANCE MEMORY LIMITED

    Inventor： Zhichao Lu ,  Liang Zhao

    IPC: G11C14/00 ,  G06N3/06 ,  G06N5/04 ,  G11C11/22 ,  G11C11/4074 ,  G11C11/56

    Abstract: Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.

    Feedback method and apparatus, terminal device, and network device
    7.
    发明授权
    Feedback method and apparatus, terminal device, and network device 有权

    公开(公告)号：US12225546B2

    公开(公告)日：2025-02-11

    申请号：US17839969

    申请日：2022-06-14

    Applicant: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.

    Inventor： Shukun Wang

    IPC: H04W72/23 ,  H04L5/00

    Abstract: The embodiments of the present disclosure provide a feedback method and apparatus, a terminal device, and a network device. The method includes: receiving, by a terminal device, Downlink Control Information (DCI) transmitted by a network device, the DCI carrying first indication information indicating a state of at least one group of secondary cells (Scells) or at least one Scell; and transmitting, by the terminal device, second indication information to the network device, the second indication information indicating that the terminal device acknowledges receipt of the first indication information.

    Information reading method, device, cable, charging system, and computer storage medium
    9.
    发明授权
    Information reading method, device, cable, charging system, and computer storage medium 有权

    公开(公告)号：US12222786B2

    公开(公告)日：2025-02-11

    申请号：US18135868

    申请日：2023-04-18

    Applicant: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.

    Inventor： Shangbo Lin

    IPC: G06F1/26

    Abstract: The present disclosure provides an information reading method, a device, a cable, a charging system, and a computer storage medium. The device includes a device control chip and a first interface. The first interface includes a first-type data signal terminal and a second-type data signal terminal. The first-type data signal terminal is connected to a power supply terminal of a communication control chip of the cable. The second-type data signal terminal is connected to a data signal terminal of the communication control chip. The device control chip is configured to control the first-type data signal terminal to be in a first output state. The first-type data signal terminal is configured to provide, when in the first output state, a first voltage to the power supply terminal, to supply power to the communication control chip.

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