公开(公告)号：US07984268B2

公开(公告)日：2011-07-19

申请号：US10898007

申请日：2004-07-23

Applicant: David T. Hass ,  Abbas Rashid

Inventor： David T. Hass ,  Abbas Rashid

IPC: G06F9/30

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/90

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US07467243B2

公开(公告)日：2008-12-16

申请号：US10930186

申请日：2004-08-31

Applicant: Abbas Rashid ,  David T. Hass

Inventor： Abbas Rashid ,  David T. Hass

IPC: G05B19/408 ,  G06F15/16

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US07305492B2

公开(公告)日：2007-12-04

申请号：US10191742

申请日：2002-07-08

Applicant: Mark Bryers ,  Elango Ganesan ,  Frederick Gruner ,  David Hass ,  Robert Hathaway ,  Ramesh Panwar ,  Ricardo Ramirez ,  Abbas Rashid ,  Mark Vilas ,  Nazar Zaidi ,  Yen Lee ,  Chau Anh Ngoc Nguyen ,  John Phillips ,  Yuhong Andy Zhou ,  Gregory G. Spurrier ,  Sankar Ramanoorthi ,  Michael Freed

Inventor： Mark Bryers ,  Elango Ganesan ,  Frederick Gruner ,  David Hass ,  Robert Hathaway ,  Ramesh Panwar ,  Ricardo Ramirez ,  Abbas Rashid ,  Mark Vilas ,  Nazar Zaidi ,  Yen Lee ,  Chau Anh Ngoc Nguyen ,  John Phillips ,  Yuhong Andy Zhou ,  Gregory G. Spurrier ,  Sankar Ramanoorthi ,  Michael Freed

IPC: G06F15/16

CPC classification number: H04L47/125 ,  H04L29/06 ,  H04L63/0485

Abstract: A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.

Abstract translation: 网络内容服务设备包括适于执行一组网络服务的一组计算元件; 以及耦合所述一组计算元件中的计算元件的交换结构。 该组网络服务包括防火墙保护，网络地址转换，互联网协议转发，带宽管理，安全套接字层操作，Web缓存，Web交换和虚拟专用网络。 在计算元件上可操作的代码实现了网络服务，并且在还包括至少一个输入/输出端口的刀片上提供计算元件。

公开(公告)号：US07082139B2

公开(公告)日：2006-07-25

申请号：US10037144

申请日：2001-12-21

Applicant: Abbas Rashid ,  Nazar Zaidi ,  Mark Bryers

Inventor： Abbas Rashid ,  Nazar Zaidi ,  Mark Bryers

IPC: H04L12/28

CPC classification number: H04L49/102 ,  H04L12/42 ,  H04L41/0896 ,  H04L49/101 ,  H04L49/201 ,  H04L49/205 ,  H04L49/25 ,  H04L49/3018

Abstract: A cross-bar switch includes a set of input ports to receive data packets and a set of sink ports in communication with the input ports to receive the data packets and forward them onto a communications link. Each sink port is adapted to concurrently receive multiple data packets targeted to the same destination or multiple destinations. For example, one sink port receives a first data packet and a second data packet. The one sink port receives at least a portion of the second data packet during a time period in which the one sink port is receiving the first data packet.

Abstract translation: 交叉开关包括一组用于接收数据分组的输入端口和与输入端口通信的一组汇接器端口，以接收数据分组并将其转发到通信链路上。 每个宿端口适于同时接收针对相同目的地或多个目的地的多个数据分组。 例如，一个宿端口接收第一数据分组和第二数据分组。 一个宿端口在一个宿端口正在接收第一数据分组的时间段期间接收第二数据分组的至少一部分。

公开(公告)号：US07065090B2

公开(公告)日：2006-06-20

申请号：US10036603

申请日：2001-12-21

Applicant: Abbas Rashid ,  Nazar Zaidi ,  Mark Bryers

Inventor： Abbas Rashid ,  Nazar Zaidi ,  Mark Bryers

IPC: H04L12/56 ,  H04L12/28

CPC classification number: H04L49/102 ,  H04L12/42 ,  H04L41/0896 ,  H04L49/101 ,  H04L49/201 ,  H04L49/205 ,  H04L49/25 ,  H04L49/3018

Abstract: A cross-bar switch includes a set of input ports and a set of sink ports in communication with the input ports. The input ports receive packets, which are snooped by the sink ports. The cross-bar switch also includes a set of port address tables. Each port address table is adapted to store data identifying a plurality of destinations supported by a sink port. For example, a first port address table is adapted to identify a plurality of destinations supported by a first sink port in the set of sink ports. When determining whether to accept a packet, a sink port considers whether the packet's destination is identified in the sink port's port address table. By supporting multiple destinations, a port address table implicitly facilitates a sink port's multicast operation.

Abstract translation: 交叉开关包括一组输入端口和一组与输入端口通信的端口端口。 输入端口接收由接收端口窥探的数据包。 交叉开关还包括一组端口地址表。 每个端口地址表适于存储识别由宿端口支持的多个目的地的数据。 例如，第一端口地址表适于识别由该汇聚端口集合中的第一宿端口支持的多个目的地。 在确定是否接受数据包时，宿端口会考虑数据包的目的地是否在接收端口的端口地址表中被识别。 通过支持多个目的地，端口地址表隐式地有助于汇聚端口的多播操作。

公开(公告)号：US20050086361A1

公开(公告)日：2005-04-21

申请号：US10930186

申请日：2004-08-31

Applicant: Abbas Rashid ,  David Hass

Inventor： Abbas Rashid ,  David Hass

IPC: G06F12/08 ,  H04L12/56 ,  G06F15/16

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20050044308A1

公开(公告)日：2005-02-24

申请号：US10930937

申请日：2004-08-31

Applicant: Abbas Rashid ,  David Hass

Inventor： Abbas Rashid ,  David Hass

IPC: G06F12/08 ,  H04L12/56 ,  H04J3/12 ,  G06F12/00

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20050033889A1

公开(公告)日：2005-02-10

申请号：US10931003

申请日：2004-08-31

Applicant: David Hass ,  Abbas Rashid

Inventor： David Hass ,  Abbas Rashid

IPC: G06F12/08 ,  H04L12/56 ,  G06F13/24

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/109 ,  H04L69/321

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US06288730B1

公开(公告)日：2001-09-11

申请号：US09378408

申请日：1999-08-20

Applicant: Jerome F. Duluk, Jr. ,  Richard E. Hessel ,  Joseph P. Grass ,  Abbas Rashid ,  Bo Hong ,  Abraham Mammen

Inventor： Jerome F. Duluk, Jr. ,  Richard E. Hessel ,  Joseph P. Grass ,  Abbas Rashid ,  Bo Hong ,  Abraham Mammen

IPC: G06T1140

CPC classification number: G06T15/20 ,  G06T1/60 ,  G06T11/001 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/30 ,  G06T15/40 ,  G06T15/50 ,  G06T15/80 ,  G06T15/83 ,  G06T15/87

Abstract: A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.

Abstract translation: 一种延迟图形流水线处理器，包括与纹理单元相关联的纹理单元和纹理存储器。 纹理单元将存储在纹理存储器中的纹理映射应用于像素片段。 纹理是MIP映射的，并且包括不同细节级别的一系列纹理贴图，每个贴图表示在距离眼点的给定距离处的纹理的外观。 纹理单元从纹理图执行三线性插值，以产生近似正确的细节水平的给定像素片段的纹理值。 纹理存储器以减少存储器访问冲突的方式存储和访问纹理数据，从而提高所述纹理单元的吞吐量。

公开(公告)号：US20110225398A1

公开(公告)日：2011-09-15

申请号：US13115012

申请日：2011-05-24

Applicant: David T. Hass ,  Abbas Rashid

Inventor： David T. Hass ,  Abbas Rashid

IPC: G06F9/312

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/90

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。