公开(公告)号：US5845071A

公开(公告)日：1998-12-01

申请号：US720368

申请日：1996-09-27

申请人： David M. Patrick ,  Alan D. Gant ,  David M. Chastain

发明人： David M. Patrick ,  Alan D. Gant ,  David M. Chastain

IPC分类号： G06F15/173 ,  G06F11/00 ,  G06F15/177 ,  G06F12/14 ,  G06F13/16

CPC分类号： G06F11/004

摘要： The multi-node multiprocessor system with globally shared memory is partitioned into groups of nodes called error containment clusters of nodes or ECCNs. The nodes would be partitioned such that an ECCN resides on a column of nodes or a row of nodes. Within each ECCN there is coherent memory sharing. Between the ECCNs, the communication is through a messaging protocol. The memory within each node is also partitioned into protected and unprotected memory. Unprotected memory is used for messaging and protected memory is used for sharing. A failure in an error containment cluster would corrupt the memory within that cluster, specifically the protected memory within that cluster and also the unprotected memory used by that cluster to communicate with the other clusters. However, the other clusters could continue to run because their protected memory would be unaffected, and could continue to communicate through the remaining unprotected memory.

摘要翻译： 具有全局共享内存的多节点多处理器系统被划分为称为节点或ECCN的容错集群的节点组。 节点将被分区，使得ECCN驻留在节点列或一行节点上。 每个ECCN内部都有一致的内存共享。 在ECCN之间，通信是通过消息协议。 每个节点内的存储器也被划分为受保护和未受保护的存储器。 无保护的内存用于消息传递，受保护的内存用于共享。 错误包含集群中的故障会破坏该集群内的内存，特别是该集群内的受保护内存，以及该集群用于与其他集群进行通信的未受保护内存。 然而，其他集群可能会继续运行，因为它们受保护的内存将不受影响，并且可以继续通过剩余的未受保护的内存进行通信。

公开(公告)号：US4868742A

公开(公告)日：1989-09-19

申请号：US206962

申请日：1988-06-09

申请人： Alan D. Gant ,  David A. Nobles ,  Thomas M. Jones ,  Arthur T. Kimmel

发明人： Alan D. Gant ,  David A. Nobles ,  Thomas M. Jones ,  Arthur T. Kimmel

IPC分类号： G06F13/26 ,  G06F13/28 ,  G06F13/364 ,  G06F13/42 ,  G06F15/17

CPC分类号： G06F13/26 ,  G06F13/28 ,  G06F13/364 ,  G06F13/4217 ,  G06F15/17

摘要： A communication bus (14) provides bidirectional data communication between a computer (12) and various peripheral units including input/output processors (18, 20) and a service processor (22). The computer includes a memory control unit (24) which is connected to a memory array (26). A central processor unit (30) is connected for data exchange with the memory control unit (24). Data blocks are transferred through the bus (14) and either originate or terminate at the memory array (26). A peripheral unit, such as the processor (18) transfers a data block by first transferring a header parcel (146) which defines an address, block length and type of function. This is transmitted to the memory control unit (24) which carries out the desired data transfer by sending or receiving sequential data parcels. An interrupt bus (16) connects each of the units of the computer system (10) including the processors (18, 20, 22) and the central processing unit (30). Any one of the units connected to the interrupt bus ( 16) can interrupt any of the other units. The interrupt process comprises sending an interrupt vector through interrupt lines (66). At the receiving unit the interrupt is identified and the appropriate function carried out. The combination of the communication bus and the interrupt bus (16) comprises an input/output bus for the computer system (10) to provide a high data bandwidth together with flexible operation.

摘要翻译： 通信总线（14）在计算机（12）和包括输入/​​输出处理器（18,20）和服务处理器（22）的各种外围单元之间提供双向数据通信。 计算机包括连接到存储器阵列（26）的存储器控​​制单元（24）。 中央处理器单元（30）被连接用于与存储器控制单元（24）进行数据交换。 数据块通过总线（14）传送，并且起始或终止于存储器阵列（26）。 诸如处理器（18）的外围单元通过首先传送定义地址，块长度和功能类型的报头包裹（146）来传送数据块。 这被发送到存储器控制单元（24），存储器控制单元（24）通过发送或接收顺序数据包来执行期望的数据传送。 中断总线（16）连接包括处理器（18,20,22）和中央处理单元（30）的计算机系统（10）的每个单元。 连接到中断总线（16）的单元中的任何一个可以中断任何其他单元。 中断过程包括通过中断线（66）发送中断向量。 在接收单元处，识别中断并执行适当的功能。 通信总线和中断总线（16）的组合包括用于计算机系统（10）的输入/输出总线，以提供高数据带宽以及灵活的操作。

公开(公告)号：US4649471A

公开(公告)日：1987-03-10

申请号：US471095

申请日：1983-03-01

申请人： Willard S. Briggs ,  Alan D. Gant ,  Parveen K. Gupta ,  Isadore S. Ferson

发明人： Willard S. Briggs ,  Alan D. Gant ,  Parveen K. Gupta ,  Isadore S. Ferson

IPC分类号： G06F13/16 ,  G06F12/06 ,  G06F13/362 ,  G06F15/78 ,  G06F13/18

CPC分类号： G06F12/0653 ,  G06F13/362

摘要： A microcomputer includes I/O ports and registers which are mapped in memory space along with RAM and ROM and in which hardware invisible to the programmer performs a bus arbitration sequence to acquire an external bus when an off-chip reference requires the bus; and in which memory space that is used for on-chip references is recovered for use in external memory by manipulating bits in the memory address.

摘要翻译： 微型计算机包括与RAM和ROM一起映射到存储器空间中的I / O端口和寄存器，并且当片外参考需要总线时，编程器不可见的硬件执行总线仲裁序列以获取外部总线; 并且其中用于片上引用的存储器空间通过操纵存储器地址中的位而被恢复用于外部存储器。

公开(公告)号：US4620275A

公开(公告)日：1986-10-28

申请号：US622451

申请日：1984-06-20

申请人： Steven J. Wallach ,  Thomas M. Jones ,  Frank J. Marshall ,  David A. Nobles ,  Kent A. Fuka ,  Steven M. Rowan ,  William H. Wallace ,  Harold W. Dozier ,  David M. Chastain ,  John W. Clark ,  Robert B. Kolstad ,  James E. Mankovich ,  Michael C. Harris ,  Jeffrey H. Gruger ,  Alan D. Gant ,  Harold D. Shelton ,  James R. Weatherford ,  Arthur T. Kimmel ,  Gary B. Gostin ,  Gilbert J. Hansen ,  John M. Golenbieski ,  Larry W. Spry ,  Gerald Matulka ,  Gaynel J. Lockhart ,  Michael E. Sydow

发明人： Steven J. Wallach ,  Thomas M. Jones ,  Frank J. Marshall ,  David A. Nobles ,  Kent A. Fuka ,  Steven M. Rowan ,  William H. Wallace ,  Harold W. Dozier ,  David M. Chastain ,  John W. Clark ,  Robert B. Kolstad ,  James E. Mankovich ,  Michael C. Harris ,  Jeffrey H. Gruger ,  Alan D. Gant ,  Harold D. Shelton ,  James R. Weatherford ,  Arthur T. Kimmel ,  Gary B. Gostin ,  Gilbert J. Hansen ,  John M. Golenbieski ,  Larry W. Spry ,  Gerald Matulka ,  Gaynel J. Lockhart ,  Michael E. Sydow

IPC分类号： G06F15/78 ,  G06F9/18

CPC分类号： G06F15/8069

摘要： A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor. In a further aspect of the computer there is produced an entry microword from a store for the immediate execution of the first microinstruction within a sequence of microinstructions. The remaining microinstructions are produced from a conventional store. This reduces the delay in the retrieval and execution of the first microinstruction. In a still further aspect of the computer there is included the logical data cache which stores data at logical addresses such that the central processor can store and retrieve data without the necessity of first making a translation from logical to physical address.

摘要翻译： 矢量处理计算机被配置为以流水线方式操作，其中每个功能单元基本上是独立的并且被设计为以最快的方式执行其操作功能。 矢量元素通过源总线从存储器，主存储器，物理缓存单元或逻辑高速缓存传送，其中元件被交替地加载到向量处理单元中。 矢量控制单元解码矢量指令，并产生用于在矢量处理单元内操作寄存器和逻辑单元的所需控制命令。 因此，矢量处理单元基本上并行地工作，使处理速率加倍。 所得到的矢量通过目的地总线传送到物理高速缓存单元，主存储器，逻辑高速缓存或输入/输出处理器。 在计算机的另一方面，产生了来自商店的入口微词，用于在微指令序列内立即执行第一微指令。 剩余的微指令是从常规商店生产的。 这减少了第一微指令的检索和执行的延迟。 在计算机的另一方面，包括逻辑数据高速缓存，其以逻辑地址存储数据，使得中央处理器可以存储和检索数据，而不需要首先进行从逻辑地址到物理地址的转换。