公开(公告)号：US20090321735A1

公开(公告)日：2009-12-31

申请号：US12555241

申请日：2009-09-08

申请人： Alberto Cestero ,  Byeongju Park ,  John M. Safran

发明人： Alberto Cestero ,  Byeongju Park ,  John M. Safran

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.

摘要翻译： 具有包括非硅化半导体材料区域的连接的反熔丝可以以降低的电压和电流进行编程，并且通过金属或硅化物从阴极电迁移到非硅化半导体材料的区域而减少产生热量，从而形成具有降低的体积电阻的合金 。 阴极和阳极优选成形为控制从哪里和哪些材料被电迁移的区域。 在编程之后，材料的额外电迁移可将反熔丝返回到高电阻状态。 反熔丝制造的过程与场效应晶体管的制造完全兼容，并且反熔丝可有利地形成在隔离结构上。

公开(公告)号：US08361887B2

公开(公告)日：2013-01-29

申请号：US13362043

申请日：2012-01-31

申请人： Alberto Cestero ,  Byeongju Park ,  John M. Safran

发明人： Alberto Cestero ,  Byeongju Park ,  John M. Safran

IPC分类号： H01L21/326

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.

摘要翻译： 具有包括非硅化半导体材料区域的连接的反熔丝可以以降低的电压和电流进行编程，并且通过金属或硅化物从阴极电迁移到非硅化半导体材料的区域来减少产生热量，从而形成具有降低的体积电阻的合金 。 阴极和阳极优选成形为控制从哪里和哪些材料电迁移的区域。 在编程之后，材料的额外电迁移可将反熔丝返回到高电阻状态。 反熔丝制造的过程与场效应晶体管的制造完全兼容，并且反熔丝可有利地形成在隔离结构上。

公开(公告)号：US20080217736A1

公开(公告)日：2008-09-11

申请号：US11683068

申请日：2007-03-07

申请人： Alberto Cestero ,  Byeongju Park ,  John M. Safran

发明人： Alberto Cestero ,  Byeongju Park ,  John M. Safran

IPC分类号： H01L29/00 ,  H01L21/44 ,  H01L21/479

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.

摘要翻译： 具有包括非硅化半导体材料区域的连接的反熔丝可以以降低的电压和电流进行编程，并且通过金属或硅化物从阴极电迁移到非硅化半导体材料的区域来减少产生热量，从而形成具有降低的体积电阻的合金 。 阴极和阳极优选成形为控制从哪里和哪些材料电迁移的区域。 在编程之后，材料的额外电迁移可将反熔丝返回到高电阻状态。 反熔丝制造的过程与场效应晶体管的制造完全兼容，并且反熔丝可有利地形成在隔离结构上。

公开(公告)号：US08590010B2

公开(公告)日：2013-11-19

申请号：US13302314

申请日：2011-11-22

申请人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

发明人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

IPC分类号： H03M13/05

CPC分类号： G06F21/73 ,  G06F21/44 ,  G06F2221/2103 ,  G09C1/00 ,  H04L9/3278 ,  H04L2209/127

摘要： A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

摘要翻译： 随机内在芯片ID生成采用保留失败签名。 使用测试设置生成第1和第2个ID，第一个设置比第二个设置的限制要大于第二个设置，在包含第二个ID位串的第一个ID位字符串中创建更多的故障。 保留暂停时间控制由BIST引擎调整的保留失败次数，其中失败号码满足预定的失败目标。 验证确认第一ID是否包含第二ID位字符串，该ID是用于认证的ID。 认证由具有中间条件的第三ID启用，使得第一ID包括第三ID位串，第三ID包括第二ID位串。 中间条件包括用于消除第1和第2 ID边界附近的位不稳定性问题的保护带。 在每次ID读取操作中改变中间条件，导致更安全的识别。

公开(公告)号：US20130133031A1

公开(公告)日：2013-05-23

申请号：US13302314

申请日：2011-11-22

申请人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

发明人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

IPC分类号： G06F21/00

CPC分类号： G06F21/73 ,  G06F21/44 ,  G06F2221/2103 ,  G09C1/00 ,  H04L9/3278 ,  H04L2209/127

摘要： A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

摘要翻译： 随机内在芯片ID生成采用保留失败签名。 使用测试设置生成第1和第2个ID，第一个设置比第二个设置的限制要大于第二个设置，在包含第二个ID位串的第一个ID位字符串中创建更多的故障。 保留暂停时间控制由BIST引擎调整的保留失败次数，其中失败号码满足预定的失败目标。 验证确认第一ID是否包含第二ID位字符串，该ID是用于认证的ID。 认证由具有中间条件的第三ID启用，使得第一ID包括第三ID位串，第三ID包括第二ID位串。 中间条件包括用于消除第1和第2 ID边界附近的位不稳定性问题的保护带。 在每次ID读取操作中改变中间条件，导致更安全的识别。

公开(公告)号：US08115275B2

公开(公告)日：2012-02-14

申请号：US12555241

申请日：2009-09-08

申请人： Alberto Cestero ,  Byeongju Park ,  John M. Safran

发明人： Alberto Cestero ,  Byeongju Park ,  John M. Safran

IPC分类号： H01L21/326

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.

摘要翻译： 具有包括非硅化半导体材料区域的连接的反熔丝可以以降低的电压和电流进行编程，并且通过金属或硅化物从阴极电迁移到非硅化半导体材料的区域来减少产生热量，从而形成具有降低的体积电阻的合金 。 阴极和阳极优选成形为控制从哪里和哪些材料电迁移的区域。 在编程之后，材料的额外电迁移可将反熔丝返回到高电阻状态。 反熔丝制造的过程与场效应晶体管的制造完全兼容，并且反熔丝可有利地形成在隔离结构上。

公开(公告)号：US20120129319A1

公开(公告)日：2012-05-24

申请号：US13362043

申请日：2012-01-31

申请人： Alberto Cestero ,  Byeongju Park ,  John M. Safran

发明人： Alberto Cestero ,  Byeongju Park ,  John M. Safran

IPC分类号： H01L21/326

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.

摘要翻译： 具有包括非硅化半导体材料区域的连接的反熔丝可以以降低的电压和电流进行编程，并且通过金属或硅化物从阴极电迁移到非硅化半导体材料的区域来减少产生热量，从而形成具有降低的体积电阻的合金 。 阴极和阳极优选成形为控制从哪里和哪些材料电迁移的区域。 在编程之后，材料的额外电迁移可将反熔丝返回到高电阻状态。 反熔丝制造的过程与场效应晶体管的制造完全兼容，并且反熔丝可有利地形成在隔离结构上。

公开(公告)号：US07674691B2

公开(公告)日：2010-03-09

申请号：US11683068

申请日：2007-03-07

申请人： Alberto Cestero ,  Byeongju Park ,  John M. Safran

发明人： Alberto Cestero ,  Byeongju Park ,  John M. Safran

IPC分类号： H01L21/326

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.

摘要翻译： 具有包括非硅化半导体材料区域的连接的反熔丝可以以降低的电压和电流进行编程，并且通过金属或硅化物从阴极电迁移到非硅化半导体材料的区域来减少产生热量，从而形成具有降低的体积电阻的合金 。 阴极和阳极优选成形为控制从哪里和哪些材料电迁移的区域。 在编程之后，材料的额外电迁移可将反熔丝返回到高电阻状态。 反熔丝制造的过程与场效应晶体管的制造完全兼容，并且反熔丝可有利地形成在隔离结构上。

公开(公告)号：US20090108400A1

公开(公告)日：2009-04-30

申请号：US11931167

申请日：2007-10-31

申请人： Alberto Cestero ,  Byeongju Park ,  John Safran

发明人： Alberto Cestero ,  Byeongju Park ,  John Safran

IPC分类号： H01L23/58 ,  H01L21/441

CPC分类号： H01L23/5252 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： An antifuse structure includes a sense pad contact region that is separate from an anode contact region and a cathode contact region. By including the sense pad contact region that is separate from the anode contact region and the cathode contact region, a programming current flow when programming the antifuse structure may travel a different pathway than a sense current flow when sensing the antifuse structure. In particular a sense current flow may avoid a depletion region created within the cathode contact region when programming the antifuse structure.

摘要翻译： 反熔丝结构包括与阳极接触区域和阴极接触区域分开的感测焊盘接触区域。 通过包括与阳极接触区域和阴极接触区域分开的感测焊盘接触区域，编程反熔丝结构时的编程电流将在检测反熔丝结构时传播与感测电流不同的通路。 特别地，当编程反熔丝结构时，感测电流可以避免在阴极接触区域内产生的耗尽区域。