公开(公告)号：US08590010B2

公开(公告)日：2013-11-19

申请号：US13302314

申请日：2011-11-22

申请人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

发明人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

IPC分类号： H03M13/05

CPC分类号： G06F21/73 ,  G06F21/44 ,  G06F2221/2103 ,  G09C1/00 ,  H04L9/3278 ,  H04L2209/127

摘要： A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

摘要翻译： 随机内在芯片ID生成采用保留失败签名。 使用测试设置生成第1和第2个ID，第一个设置比第二个设置的限制要大于第二个设置，在包含第二个ID位串的第一个ID位字符串中创建更多的故障。 保留暂停时间控制由BIST引擎调整的保留失败次数，其中失败号码满足预定的失败目标。 验证确认第一ID是否包含第二ID位字符串，该ID是用于认证的ID。 认证由具有中间条件的第三ID启用，使得第一ID包括第三ID位串，第三ID包括第二ID位串。 中间条件包括用于消除第1和第2 ID边界附近的位不稳定性问题的保护带。 在每次ID读取操作中改变中间条件，导致更安全的识别。

公开(公告)号：US20130133031A1

公开(公告)日：2013-05-23

申请号：US13302314

申请日：2011-11-22

申请人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

发明人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

IPC分类号： G06F21/00

CPC分类号： G06F21/73 ,  G06F21/44 ,  G06F2221/2103 ,  G09C1/00 ,  H04L9/3278 ,  H04L2209/127

摘要： A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

摘要翻译： 随机内在芯片ID生成采用保留失败签名。 使用测试设置生成第1和第2个ID，第一个设置比第二个设置的限制要大于第二个设置，在包含第二个ID位串的第一个ID位字符串中创建更多的故障。 保留暂停时间控制由BIST引擎调整的保留失败次数，其中失败号码满足预定的失败目标。 验证确认第一ID是否包含第二ID位字符串，该ID是用于认证的ID。 认证由具有中间条件的第三ID启用，使得第一ID包括第三ID位串，第三ID包括第二ID位串。 中间条件包括用于消除第1和第2 ID边界附近的位不稳定性问题的保护带。 在每次ID读取操作中改变中间条件，导致更安全的识别。

公开(公告)号：US06747890B1

公开(公告)日：2004-06-08

申请号：US10249347

申请日：2003-04-02

申请人： Toshiaki Kirihata ,  Subramanian S. Iyer ,  John W. Golz

发明人： Toshiaki Kirihata ,  Subramanian S. Iyer ,  John W. Golz

IPC分类号： G11C1124

CPC分类号： H01L27/10844 ,  G11C2207/104 ,  H01L27/108 ,  H01L27/11

摘要： Gain cells adapted to trench capacitor technology and memory array configured with these gain cells are described. The 3T and 2T gain cells of the present invention include a trench capacitor attached to a storage node such that the storage voltage is maintained for a long retention time. The gate of the gain transistor and the trench capacitor are placed alongside the read and write wordline. This arrangement makes it possible to have the gain transistor directly coupled to the trench capacitor, resulting in a smaller cell size. The memory cell includes a first transistor provided with a gate, a source, and a drain respectively coupled to a read wordline, a first node, and a read bitline; a second transistor having a gate, a source, and a drain respectively coupled to a storage node, to a voltage source, and to the first node; a third transistor having a gate, a source, and a drain respectively coupled to a write wordline, the storage node, and a write bitline; and a capacitor having a first terminal connected to the storage node and a second terminal connected to a voltage source.

摘要翻译： 描述适用于沟槽电容器技术的增益单元和配置有这些增益单元的存储器阵列。 本发明的3T和2T增益单元包括连接到存储节点的沟槽电容器，使得存储电压保持长的保留时间。 增益晶体管的栅极和沟槽电容器放置在读写字线旁边。 这种布置使得可以使增益晶体管直接耦合到沟槽电容器，导致更小的单元尺寸。 存储单元包括：第一晶体管，其设置有分别耦合到读字线，第一节点和读位线的栅极，源极和漏极; 第二晶体管，其具有分别耦合到存储节点的栅极，源极和漏极，电压源以及所述第一节点; 第三晶体管，具有分别耦合到写入字线，存储节点和写入位线的栅极，源极和漏极; 以及电容器，其具有连接到存储节点的第一端子和连接到电压源的第二端子。

公开(公告)号：US09184129B2

公开(公告)日：2015-11-10

申请号：US13004129

申请日：2011-01-11

申请人： Byeongju Park ,  Subramanian S. Iyer ,  Chandrasekharan Kothandaraman

发明人： Byeongju Park ,  Subramanian S. Iyer ,  Chandrasekharan Kothandaraman

IPC分类号： H01L23/525 ,  H01L27/112 ,  G11C17/16

CPC分类号： H01L23/5252 ,  G11C17/165 ,  G11C2229/763 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/928 ,  H01L2924/00

摘要： The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.

摘要翻译： 本发明提供了具有集成加热元件的反熔丝结构及其编程方法，反熔丝结构包括第一和第二导体以及形成在导体之间的介电层，其中一个或两个导体用作传统的反熔丝导体和 作为用于在编程期间直接加热反熔丝介电层的加热元件。

公开(公告)号：US08629017B2

公开(公告)日：2014-01-14

申请号：US13417900

申请日：2012-03-12

申请人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

发明人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

IPC分类号： H01L21/8242

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/945

摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

摘要翻译： 提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和 内电极 以及位于沟槽电容器上方的半导体器件。 半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。 存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

公开(公告)号：US20130009277A1

公开(公告)日：2013-01-10

申请号：US13617576

申请日：2012-09-14

申请人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Geng Wang

发明人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/06

CPC分类号： H01L29/945 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/66181

摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

摘要翻译： 公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。 该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。 该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

公开(公告)号：US08298914B2

公开(公告)日：2012-10-30

申请号：US12194198

申请日：2008-08-19

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

IPC分类号： H01L21/4763

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83121 ,  H01L2224/83895 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

摘要： A method is provided for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer. Also provided is a tangible computer readable medium encoded with a program that comprises instructions for performing such a method.

摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。 第一有源电路层晶片被结合到界面晶片。 然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。 包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。 接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。 还提供了一种用包括用于执行这种方法的指令的程序编码的有形计算机可读介质。

公开(公告)号：US08188528B2

公开(公告)日：2012-05-29

申请号：US12437242

申请日：2009-05-07

申请人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

发明人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

IPC分类号： H01L27/108

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/945

摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

摘要翻译： 提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和 内电极 以及位于沟槽电容器上方的半导体器件。 半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。 存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

公开(公告)号：US08129256B2

公开(公告)日：2012-03-06

申请号：US12194065

申请日：2008-08-19

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

IPC分类号： H01L21/30

CPC分类号： H01L27/105 ,  H01L24/11 ,  H01L27/0688 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 根据该方法，提供第一有源电路层晶片。 第一有源电路层晶片包括由P层覆盖的P +部分，并且P层包括有源电路。 第一有源电路层晶片面向下接合到包括第一布线层的接口晶片，然后相对于第一有源电路层晶片的P层选择性地去除第一有源电路层晶片的P +部分 。 接下来，在P-层的背面上制造布线层。 还提供了用用于制造3D集成电路结构的程序编码的有形计算机可读介质和3D集成电路结构。

公开(公告)号：US20110187407A1

公开(公告)日：2011-08-04

申请号：US12696104

申请日：2010-01-29

申请人： Subramanian S. Iyer ,  Chandrasekharan Kothandaraman ,  Gerard M. Salem

发明人： Subramanian S. Iyer ,  Chandrasekharan Kothandaraman ,  Gerard M. Salem

IPC分类号： H03K19/173 ,  G01R31/02

CPC分类号： G01R31/02 ,  H03K19/173

摘要： Embodiments of the invention provides a method, device, and system for programming an electromigration fuse (eFuse) using a radio frequency (RF) signal. A first aspect of the invention provides a method of testing circuitry on a semiconductor chip, the method comprising: receiving a radio frequency (RF) signal using at least one antenna on the semiconductor chip; powering circuitry on the semiconductor chip using the RF signal; activating a built-in self test (BIST) engine within the circuitry; determining whether a fault exists within the circuitry using the BIST; and programming an electromigration fuse (eFuse) to alter the circuitry in response to a fault being determined to exist.

摘要翻译： 本发明的实施例提供了一种使用射频（RF）信号编程电迁移保险丝（eFuse）的方法，装置和系统。 本发明的第一方面提供了一种在半导体芯片上测试电路的方法，该方法包括：使用半导体芯片上的至少一个天线接收射频（RF）信号; 使用RF信号对半导体芯片供电; 激活电路内的内置自检（BIST）引擎; 确定使用BIST的电路内是否存在故障; 以及编程电迁移保险丝（eFuse）以响应于确定存在的故障来改变电路。