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公开(公告)号：US09647623B2
公开(公告)日：2017-05-09
申请号：US12571092
申请日：2009-09-30
CPC分类号： H04B1/16 , H03G3/3068
摘要： A signal processor for a radio frequency (RF) receiver includes a plurality of distributed signal processing elements, in which a first one receives an input signal and a last one provides an output signal, and a plurality of gain elements interspersed between pairs of said plurality of distributed signal processing elements. The signal processor also includes a like plurality of peak detectors coupled to outputs of corresponding ones of said plurality of gain elements, and an automatic gain controller having inputs coupled to outputs of each of the peak detectors, and outputs coupled to each of the plurality of gain elements. The automatic gain controller independently controls each of the plurality of gain elements to form a like plurality of independent automatic gain control (AGC) loops.
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公开(公告)号：US20130117790A1
公开(公告)日：2013-05-09
申请号：US13344143
申请日：2012-01-05
CPC分类号： H03M3/394 , H03M3/396 , H03M3/398 , H03M3/40 , H03M3/448 , H03M3/45 , H03M3/452 , H03M3/454 , H04N21/6112 , H04N21/6118 , H04N21/6143
摘要： A method of configuring an analog-to-digital converter (ADC) includes configuring the ADC to operate in one of a low-pass filter mode and a band-pass filter mode according to a value of a control signal. In at least one embodiment, the method further includes configuring an integrator gain of the ADC and a feed-forward gain of the ADC based on selection of one of a low-intermediate frequency (LIF) mode and a zero-intermediate frequency (ZIF) mode.
摘要翻译： 配置模数转换器（ADC）的方法包括根据控制信号的值将ADC配置为以低通滤波器模式和带通滤波器模式之一工作。 在至少一个实施例中，该方法还包括基于选择低中频（LIF）模式和零中频（ZIF）之一来配置ADC的积分器增益和ADC的前馈增益， 模式。
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公开(公告)号：US08428536B2
公开(公告)日：2013-04-23
申请号：US12323040
申请日：2008-11-25
CPC分类号： H04B1/28 , H03G3/3068
摘要： A receiver (100) includes a first element (110) with a signal input, a control input, a signal output, and gain steps of a first magnitude, a signal processing circuit (120-168) with a signal input coupled to the first element, and a signal output, a second element (180) that has a signal input coupled to signal processing circuit, a control input, a signal output, and gain steps of a second magnitude smaller than the first magnitude, and a controller (180) that has a control output coupled to the first element (110), a control output coupled to the second element (180), and that adjusts receiver (100) gain by changing the first element (110) gain by a first magnitude, changing the second element (180) gain by substantially an inverse first magnitude, and subsequently changing the gain of the second element (180) by steps of the second magnitude to achieve a desired gain.
摘要翻译： 接收器（100）包括具有信号输入的第一元件（110），控制输入，信号输出和第一幅度的增益步长，信号处理电路（120-168），信号输入端与第一 元件和信号输出，具有耦合到信号处理电路的信号输入的第二元件（180），小于第一幅度的第二幅度的控制输入，信号输出和增益步骤，以及控制器（180） ），其具有耦合到所述第一元件（110）的控制输出，耦合到所述第二元件（180）的控制输出，并且通过将所述第一元件（110）增益改变第一量值来调整接收器（100）增益， 第二元件（180）通过基本上相反的第一幅度增益，随后通过第二幅度的步长来改变第二元件（180）的增益，以实现期望的增益。
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公开(公告)号：US08126420B2
公开(公告)日：2012-02-28
申请号：US12005513
申请日：2007-12-27
IPC分类号： H04B1/10
摘要： In one embodiment, the present invention includes a method for digitizing a phase noise value indicative of a level of phase noise present in a LO signal and downconverting an RF signal to a second frequency signal using the LO signal. This downconversion can cause the phase noise to be transferred to the second frequency signal. The method may thus further include removing the phase noise from the second frequency signal using the digitized phase noise value.
摘要翻译： 在一个实施例中，本发明包括一种数字化表示LO信号中存在的相位噪声电平的相位噪声值并使用LO信号将RF信号下变频为第二频率信号的方法。 该下变频可导致相位噪声被传送到第二频率信号。 因此，该方法可以进一步包括使用数字化相位噪声值从第二频率信号中去除相位噪声。
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5.发明申请Signal Processor Suitable for Low Intermediate Frequency (LIF) or Zero Intermediate Frequency (ZIF) Operation 有权信号处理器适用于低中频（LIF）或零中频（ZIF）操作公开(公告)号：US20110076977A1
公开(公告)日：2011-03-31
申请号：US12571092
申请日：2009-09-30
IPC分类号： H04B1/06
CPC分类号： H04B1/16 , H03G3/3068
摘要： A signal processor for a radio frequency (RF) receiver includes a plurality of distributed signal processing elements, in which a first one receives an input signal and a last one provides an output signal, and a plurality of gain elements interspersed between pairs of said plurality of distributed signal processing elements. The signal processor also includes a like plurality of peak detectors coupled to outputs of corresponding ones of said plurality of gain elements, and an automatic gain controller having inputs coupled to outputs of each of the peak detectors, and outputs coupled to each of the plurality of gain elements. The automatic gain controller independently controls each of the plurality of gain elements to form a like plurality of independent automatic gain control (AGC) loops.
摘要翻译： 一种用于射频（RF）接收机的信号处理器包括多个分布式信号处理元件，其中第一个接收输入信号，最后一个提供输出信号，并且多个增益元素散布在所述多个 的分布式信号处理元件。 信号处理器还包括耦合到所述多个增益元件中对应的增益元件的相应输出端的相同的多个峰值检测器，以及具有耦合到每个峰值检测器的输出的输入的自动增益控制器，以及耦合到多个 获得元素。 自动增益控制器独立地控制多个增益元件中的每一个以形成相同的多个独立的自动增益控制（AGC）回路。
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公开(公告)号：US20110065411A1
公开(公告)日：2011-03-17
申请号：US12947285
申请日：2010-11-16
IPC分类号： H04B1/30
CPC分类号： H04B1/16 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D2200/0025 , H03D2200/0084 , H03D2200/0086 , H04N5/455
摘要： In one embodiment, the present invention includes a method for receiving a radio frequency (RF) signal and mixing the RF signal with a master clock to obtain a mixed signal, cyclically rotating the mixed signal to each of N gain stages for at least one cycle of the master clock, and summing the outputs of the N gain stages to provide an output signal.
摘要翻译： 在一个实施例中，本发明包括一种用于接收射频（RF）信号并将RF信号与主时钟混合以获得混合信号的方法，将混合信号周期性地旋转至N个增益级中的每一个至少一个周期 并且对N个增益级的输出进行求和以提供输出信号。
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公开(公告)号：US07756504B2
公开(公告)日：2010-07-13
申请号：US11824417
申请日：2007-06-29
IPC分类号： H04B1/26
CPC分类号： H03D7/00 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0084 , H03D2200/0086
摘要： In one embodiment, the present invention includes a mixer circuit to receive and generate a mixed signal from a radio frequency (RF) signal and a master clock signal, a switch stage coupled to an output of the mixer circuit to rotatingly switch the mixed signal to multiple gain stages coupled to the switch stage, and a combiner to combine an output of the gain stages.
摘要翻译： 在一个实施例中，本发明包括一个混频器电路，用于接收和产生来自射频（RF）信号和主时钟信号的混合信号，耦合到混频器电路的输出的开关级，以将混合信号旋转切换到 耦合到开关级的多个增益级，以及组合器，以组合增益级的输出。
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公开(公告)号：US07426376B2
公开(公告)日：2008-09-16
申请号：US11172475
申请日：2005-06-30
CPC分类号： H04B1/30 , H03G3/3068 , H04B1/0003 , H04B1/109
摘要： An apparatus includes a semiconductor package, a radio receiver and a processor. The radio receiver is located in the semiconductor package and includes at least one gain stage. The processor is located in the semiconductor package to execute stored instructions to control the gain stage(s).
摘要翻译： 一种装置包括半导体封装，无线电接收器和处理器。 无线电接收机位于半导体封装中并且包括至少一个增益级。 处理器位于半导体封装中以执行存储的指令以控制增益级。
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9.发明授权公开(公告)号：US08874060B2
公开(公告)日：2014-10-28
申请号：US12641540
申请日：2009-12-18
CPC分类号： H04B1/0007
摘要： A radio frequency (RF) receiver with frequency planning includes an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal, and is controllable to adjust a frequency of the clock signal to a selected one of a predetermined number of frequencies within a predetermined frequency range in response to the clock control signal.
摘要翻译： 具有频率规划的射频（RF）接收机包括模拟接收机，数字处理器和时钟合成器。 模拟接收器具有用于接收RF输入信号的输入端和用于提供数字中频（IF）信号的输出端。 数字处理器具有用于接收数字IF信号的第一输入端，用于接收时钟信号的第二输入端，用于提供中频输出信号的信号输出端和用于提供时钟控制信号的控制输出端。 时钟合成器具有用于接收时钟控制信号的输入端和用于提供时钟信号的输出端，并且可控制地将时钟信号的频率调整到预定频率范围内的预定频率范围内选定的一个频率，作为响应 到时钟控制信号。
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公开(公告)号：US08781428B2
公开(公告)日：2014-07-15
申请号：US12715728
申请日：2010-03-02
CPC分类号： H03L7/06
摘要： A frequency synthesizer includes a controlled oscillator configured to extend a temperature range and phase noise of the synthesizer without compromising the frequency coverage of the synthesizer. The frequency synthesizer also includes bias generation circuitry that sets a bias current of a charge pump to reduce bandwidth variations of the synthesizer. The frequency synthesizer further includes switching circuitry to dynamically turn a charge pump on and off to reduce effects of current leakage in the charge pump.
摘要翻译： 频率合成器包括受控振荡器，其被配置为在不损害合成器的频率覆盖的情况下延长合成器的温度范围和相位噪声。 频率合成器还包括偏置产生电路，其设置电荷泵的偏置电流以减少合成器的带宽变化。 频率合成器还包括开关电路，以动态地打开和关闭电荷泵，以减少电荷泵中电流泄漏的影响。
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