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公开(公告)号：US09960785B1
公开(公告)日：2018-05-01
申请号：US15480905
申请日：2017-04-06
IPC分类号： H03M3/00
摘要： A latency associated with a receiver circuit, e.g., radio receiver circuit, can be reduced by applying digital data from an analog signal received by a receiver, e.g., a radio receiver, to an automatic gain control circuit without first using a decimation and digital filtering process, which can minimize or eliminate significant latency associated with the decimation and filtering process.
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公开(公告)号：US09935649B1
公开(公告)日：2018-04-03
申请号：US15681710
申请日：2017-08-21
发明人： Axel Thomsen , Chao Yang , Xiaodong Wang
CPC分类号： H03M3/452 , H03K5/24 , H03M1/002 , H03M1/0854 , H03M1/368
摘要： A quantizer including passive summers, dynamic comparators and a clock generator. Each passive summer samples the input voltages and a reference voltage scaled by one of multiple graduated gains, and subtracts the scaled reference voltage from the sum of the input voltages. The graduated gains divide a predetermined voltage range into multiple voltage subranges, each between sequential pairs of the passive summers. The dynamic comparators compare each sequential pair of passive summer output voltages according to multiple splitting ratios and provide corresponding quantization bits. The dynamic comparators are activated in groups to reduce comparator kickback. Each dynamic comparator recharges the passive summer output voltages coupled to its inputs back to their initial voltage values to reduce kickback residual. The passive summers eliminate the need for a resistor string to generate the reference voltages. Staggered activation and comparator recharging replace preamplifiers used to suppress kickback and kickback residuals.
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公开(公告)号：US09748969B1
公开(公告)日：2017-08-29
申请号：US15098988
申请日：2016-04-14
发明人： Elmar Bach , Patrizia Greco , Wiesbauer Andreas
IPC分类号： H03M3/00
摘要： In accordance with an embodiment, a method of operating an oversampled data converter having a switched-capacitor (SC) integrator includes operating the oversampled data converter in a gain calibration mode; applying a first voltage to a feedback port of the SC integrator to form a feedback voltage, and during a first clock phase the method further includes applying the first voltage to a first series capacitor via the input port when an output of the oversampled data converter is in a first state; applying a bypass voltage to the first series capacitor when the output of the oversampled data converter is an a second state and applying the first voltage to a second series capacitor via the feedback port with a polarity based on the output of the oversampled data converter, and during a second clock phase the method includes integrating charges of the first series capacitor and the second series capacitor.
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公开(公告)号：US20170207796A1
公开(公告)日：2017-07-20
申请号：US15405628
申请日：2017-01-13
发明人： Young Kyun CHO , Bong Hyuk PARK
CPC分类号： H03M3/454 , H03H11/1204 , H03H11/1291 , H03M3/422 , H03M3/43 , H03M3/452 , H03M3/464
摘要： A third-order loop filter for a delta signal modulator comprises a single operational amplifier, and a resistor-capacitor network including a plurality of capacitors and a plurality of resistors which are connected to the operational amplifier, and satisfy a third-order transfer function.
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公开(公告)号：US09467163B1
公开(公告)日：2016-10-11
申请号：US15079556
申请日：2016-03-24
发明人： Eiki Imaizumi
IPC分类号： H03M3/00
摘要： A high-order delta-sigma modulator is realized with amplifying/integrating circuits each having a small circuit scale, to thereby provide a small-size and low-power consumption delta-sigma modulator having a high precision. The delta-sigma modulator including the amplifying/integrating circuits connected in series in a plurality of stages has a delta-sigma modulator configuration in which one of adjacent amplifying/integrating circuits includes a delay integrating circuit and another thereof includes a non-delay integrating circuit. In an actual circuit, one amplifying circuit is operated in a time division manner to be shared between the adjacent amplifying/integrating circuits. The circuit scale is reduced in this way.
摘要翻译： 利用具有小电路规模的放大/积分电路来实现高阶Δ-Σ调制器，从而提供具有高精度的小尺寸和低功耗的Δ-Σ调制器。 包括在多级中串联连接的放大/积分电路的Δ-Δ调制器具有Δ-Σ调制器配置，其中相邻放大/积分电路中的一个包括延迟积分电路，另一个包括非延迟积分电路 。 在实际电路中，一个放大电路以时分方式工作，以便在相邻的放大/积分电路之间共享。 以这种方式减小电路规模。
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公开(公告)号：US09143092B2
公开(公告)日：2015-09-22
申请号：US13325847
申请日：2011-12-14
CPC分类号： H03K17/08104 , H03F1/523 , H03F3/393 , H03F3/45179 , H03F2200/261 , H03M3/34 , H03M3/43 , H03M3/452
摘要： A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed.
摘要翻译： 通过提供具有Vinp和Vinn作为差分输入的输入斩波器，具有可以高于电源电压的共模输入电压的差分输入Vinp和Vinn的差分信号传送方法，提供输出斩波器，电容耦合 将输入斩波器的差分输出Voutp和Voutn输出到输出斩波器的差分输入端，将时钟电容耦合到输入斩波器并将时钟耦合到输出斩波器，时钟具有与第一相位相反的第一相位和第二相位 第一相耦合到第一晶体管和第二晶体管的栅极，第二相耦合到第三和第四晶体管的栅极，并且提供第一至第四晶体管的栅极的过电压保护。 公开了各种实施例。
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公开(公告)号：US20150171888A1
公开(公告)日：2015-06-18
申请号：US14558217
申请日：2014-12-02
申请人： NXP B.V.
IPC分类号： H03M3/00
摘要： Proposed is a sigma-delta modulator circuit. The circuit comprises a loopfilter having at least one integrator or resonator section; and a feed-forward path adapted to provide a feed-forward signal to the output of the at least one integrator or resonator section via a filter.
摘要翻译： 提出了一种Σ-Δ调制器电路。 该电路包括具有至少一个积分器或谐振器部分的环路滤波器; 以及前馈路径，其适于经由滤波器向所述至少一个积分器或谐振器部分的输出提供前馈信号。
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公开(公告)号：US09019136B2
公开(公告)日：2015-04-28
申请号：US14097451
申请日：2013-12-05
申请人： MediaTek Inc.
发明人： Chen-Yen Ho , Hung-Chieh Tsai , Yu-Hsin Lin
摘要： A sigma-delta modulator is provided for generating a digital output signal. The sigma-delta modulator is used to generate a digital output signal. The sigma-delta modulator includes a multi-stage loop filter and a quantizer. The multi-stage loop filter receives an analog input signal and generates an integrated output signal according to the analog input signal. The quantizer is coupled to the multi-stage loop filter. The quantizer receives the integrated output signal and quantizes the integrated output signal to generate the digital output signal. Different feed-forward paths of the sigma-delta modulator are available for different frequency bands.
摘要翻译： 提供Σ-Δ调制器用于产生数字输出信号。 Σ-Δ调制器用于产生数字输出信号。 Σ-Δ调制器包括多级环路滤波器和量化器。 多级环路滤波器接收模拟输入信号，并根据模拟输入信号产生积分输出信号。 量化器耦合到多级环路滤波器。 量化器接收积分输出信号并量化积分输出信号以产生数字输出信号。 Σ-Δ调制器的不同前馈路径可用于不同的频带。
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公开(公告)号：US08704581B2
公开(公告)日：2014-04-22
申请号：US12105545
申请日：2008-04-18
申请人： Lennart K-A Mathe
发明人： Lennart K-A Mathe
CPC分类号： H03H19/004 , H03M3/34 , H03M3/452
摘要： A switched capacitor circuit employs a single operational amplifier to implement both an integrator and a summer. One input signal is routed to the input of the operational amplifier through (1) one or more integration branches, and (2) one or more first summing branches. A second input signal is routed to the input of the operational amplifier through one or more second summing branches. Each of the branches includes a capacitor and a number of switches controlled by different clock phases. The switched capacitor circuit may be single-ended or differential. The circuit may be used in an access terminal of a cellular communication system. The access terminal may operate under a code division multiple access (CDMA) communication standard.
摘要翻译： 开关电容器电路采用单个运算放大器来实现积分器和夏季。 一个输入信号通过（1）一个或多个积分分支路由到运算放大器的输入，以及（2）一个或多个第一求和分支。 第二输入信号通过一个或多个第二加法分支路由到运算放大器的输入端。 每个分支包括电容器和由不同时钟相位控制的多个开关。 开关电容电路可以是单端或差分。 该电路可以用在蜂窝通信系统的接入终端中。 接入终端可以在码分多址（CDMA）通信标准下工作。
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公开(公告)号：US20140035769A1
公开(公告)日：2014-02-06
申请号：US13565715
申请日：2012-08-02
申请人： Omid Rajaee , Liang Dai
发明人： Omid Rajaee , Liang Dai
IPC分类号： H03M3/00
CPC分类号： H03M3/452
摘要： A low distortion feed forward delta sigma modulator includes a first adder configured to receive a feedback signal and an input signal. The modulator also includes a first integrator configured to receive an output from the first adder, and a second integrator configured to receive an output from the first integrator. The modulator further includes a second adder configured to receive a second integrated path from the second integrator, a first integrating path from the first integrator and a first summing path from the input signal. The modulator also has a last integrator configured to receive an output from the second adder.
摘要翻译： 低失真前馈ΔΣ调制器包括被配置为接收反馈信号和输入信号的第一加法器。 调制器还包括被配置为接收来自第一加法器的输出的第一积分器和被配置为接收来自第一积分器的输出的第二积分器。 调制器还包括第二加法器，其被配置为从第二积分器接收第二集成路径，来自第一积分器的第一积分路径和来自输入信号的第一求和路径。 调制器还具有配置为接收来自第二加法器的输出的最后一个积分器。
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