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公开(公告)号：US08467473B2
公开(公告)日：2013-06-18
申请号：US11395907
申请日：2006-03-31
CPC分类号： H04B1/406 , H03F3/24 , H04B2001/0408 , H04L27/0008
摘要： Various embodiments are disclosed relating to power control techniques for wireless transmitters. In an example embodiment, an apparatus is provided that may include a digital-to-analog converter (DAC) adapted to convert a digital amplitude signal to an analog amplitude signal during a first transmission mode and adapted to convert a digital power level signal to an analog power level signal during a second transmission mode.
摘要翻译： 公开了关于无线发射机的功率控制技术的各种实施例。 在一个示例性实施例中，提供了一种可以包括数模转换器（DAC）的装置，其适于在第一传输模式期间将数字幅度信号转换为模拟幅度信号，并且适于将数字功率电平信号转换为 在第二传输模式期间的模拟功率电平信号。
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公开(公告)号：US08406692B2
公开(公告)日：2013-03-26
申请号：US12880937
申请日：2010-09-13
申请人： Alireza Zolfaghari
发明人： Alireza Zolfaghari
CPC分类号： H03F3/24 , H03C5/00 , H03F1/0205 , H03F1/0211 , H03F1/0277 , H03F2200/111 , H03F2200/321 , H03F2200/324 , H03F2200/333 , H03F2200/504 , H03F2200/541 , H04B1/0483 , H04B2001/0408
摘要： Various embodiments are disclosed relating to wireless systems, and also relating to transmitter amplifiers, such as, for example, polar transmitter amplifiers with variable output power. According to an example embodiment, a circuit is provided including a plurality of selectable amplifier cells. Each amplifier cell may receive a phase or frequency modulated signal and an amplitude modulated signal. Each amplifier cell may output a signal based upon a combination of the received amplitude modulated signal and the received phase or frequency modulated signal if the amplifier cell is selected. The circuit may provide a variable output current or output power based upon the selection of one or more of the amplifier cells.
摘要翻译： 公开了与无线系统相关的各种实施例，并且还涉及发射机放大器，例如具有可变输出功率的极性发射机放大器。 根据示例实施例，提供了包括多个可选放大器单元的电路。 每个放大器单元可以接收相位或频率调制信号和幅度调制信号。 如果放大器单元被选择，每个放大器单元可以基于所接收的幅度调制信号和接收的相位或频率调制信号的组合来输出信号。 该电路可以基于一个或多个放大器单元的选择来提供可变输出电流或输出功率。
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公开(公告)号：US07848725B2
公开(公告)日：2010-12-07
申请号：US11824663
申请日：2007-07-02
申请人： Alireza Zolfaghari , Hooman Darabi
发明人： Alireza Zolfaghari , Hooman Darabi
IPC分类号： H04B1/06
CPC分类号： H03L7/093 , H03L7/0891 , H03L7/18
摘要： A phase locked loop (PLL) a phase detector, a charge pump, a loop filter, a controlled oscillator, and a feedback divider. The phase detector is coupled to produce a difference signal based on a difference between phase of a reference oscillation and phase of a feedback oscillation. The charge pump is coupled to convert the difference signal into an up-signal or a down signal. The loop filter coupled to filter the up signal or the down signal to produce a control signal. The controlled oscillator is coupled to generate an output oscillation based on the control signal. The feedback divider is coupled to generate the feedback oscillation from the output oscillation based on a divider value. The loop filter includes a first resistor-capacitor circuit and a second resistor-capacitor circuit. The first resistor-capacitor circuit is calibrated using a first calibration technique and the second resistor-capacitor circuit is calibrated using a second calibration technique.
摘要翻译： 锁相环（PLL），相位检测器，电荷泵，环路滤波器，受控振荡器和反馈分压器。 相位检测器被耦合以基于参考振荡的相位与反馈振荡的相位之间的差产生差分信号。 电荷泵被耦合以将差信号转换成上信号或下信号。 该滤波器被耦合以对上行信号或下降信号进行滤波以产生控制信号。 受控振荡器被耦合以基于控制信号产生输出振荡。 反馈分压器被耦合以基于分频器值从输出振荡产生反馈振荡。 环路滤波器包括第一电阻 - 电容电路和第二电阻 - 电容电路。 使用第一校准技术校准第一电阻器电容器电路，并且使用第二校准技术校准第二电阻器电容器电路。
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公开(公告)号：US20100303172A1
公开(公告)日：2010-12-02
申请号：US12473571
申请日：2009-05-28
申请人： Alireza Zolfaghari , Hooman Darabi , Ahmad Mirzaei
发明人： Alireza Zolfaghari , Hooman Darabi , Ahmad Mirzaei
CPC分类号： H04L27/0008 , H04B1/0475
摘要： A transmitter operates in different modulation modes to support both GSM/EDGE and WCDMA cellular telephony applications. The transmitter modulates an outgoing signal to produce a complex modulated signal in a first modulation mode and a constant or variable envelope modulated signal in a second modulation mode. A local oscillation generator and mixer operate to up-convert the complex modulated signal to produce a modulated RF signal in the first modulation mode and to up-convert the phase component of the constant or variable envelope modulated signal to an RF phase signal and mix the RF phase signal with the envelope component thereof to produce the modulated RF signal in the second modulation mode.
摘要翻译： 发射机以不同的调制模式工作，以支持GSM / EDGE和WCDMA蜂窝电话应用。 发射机调制输出信号以在第一调制模式中产生复调制信号，并以第二调制模式调制恒定或可变包络调制信号。 本地振荡发生器和混频器用于上变频复调制信号以在第一调制模式中产生经调制的RF信号，并将恒定或可变包络调制信号的相位分量上变频为RF相位信号，并将 RF相位信号及其包络分量，以在第二调制模式中产生经调制的RF信号。
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公开(公告)号：US20100135434A1
公开(公告)日：2010-06-03
申请号：US12702198
申请日：2010-02-08
申请人： Alireza Zolfaghari , Hooman Darabi
发明人： Alireza Zolfaghari , Hooman Darabi
IPC分类号： H04L27/00
CPC分类号： H03L7/093 , H03L7/0891 , H03L7/18
摘要： A phase locked loop (PLL) a phase detector, a charge pump, a loop filter, a controlled oscillator, and a feedback divider. The phase detector is coupled to produce a difference signal based on a difference between phase of a reference oscillation and phase of a feedback oscillation. The charge pump is coupled to convert the difference signal into an up-signal or a down signal. The loop filter coupled to filter the up signal or the down signal to produce a control signal. The controlled oscillator is coupled to generate an output oscillation based on the control signal. The feedback divider is coupled to generate the feedback oscillation from the output oscillation based on a divider value. The loop filter includes a first resistor-capacitor circuit and a second resistor-capacitor circuit. The first resistor-capacitor circuit is calibrated using a first calibration technique and the second resistor-capacitor circuit is calibrated using a second calibration technique.
摘要翻译： 锁相环（PLL），相位检测器，电荷泵，环路滤波器，受控振荡器和反馈分压器。 相位检测器被耦合以基于参考振荡的相位与反馈振荡的相位之间的差产生差分信号。 电荷泵被耦合以将差信号转换成上信号或下信号。 该滤波器被耦合以对上行信号或下降信号进行滤波以产生控制信号。 受控振荡器被耦合以基于控制信号产生输出振荡。 反馈分压器被耦合以基于分频器值从输出振荡产生反馈振荡。 环路滤波器包括第一电阻 - 电容电路和第二电阻 - 电容电路。 使用第一校准技术校准第一电阻器电容器电路，并且使用第二校准技术校准第二电阻器电容器电路。
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公开(公告)号：US20090189687A1
公开(公告)日：2009-07-30
申请号：US12020132
申请日：2008-01-25
申请人： Ahmad Mirzaei , Alireza Zolfaghari , Hooman Darabi
发明人： Ahmad Mirzaei , Alireza Zolfaghari , Hooman Darabi
CPC分类号： H03H11/0466
摘要： A circuit (e.g., a reconstruction filtering circuit) may include a single operational amplifier (op-amp) that is arranged to receive a voltage input and that is arranged to have a biasing of constant gmR, a first device capacitor that is operatively coupled to an output of the single op-amp, a first resistor that is operatively coupled to the first device capacitor, a second device capacitor that is operatively coupled to the first resistor, and a mirror device that is operatively coupled to the second device capacitor, where the mirror device is arranged to provide a feedback loop as a feedback input to the single op-amp and that is arranged to provide a current output.
摘要翻译： 电路（例如，重构滤波电路）可以包括单个运算放大器（运算放大器），其被布置为接收电压输入并且被布置为具有恒定的gmR的偏置，第一器件电容器可操作地耦合到 单个运算放大器的输出，可操作地耦合到第一器件电容器的第一电阻器，可操作地耦合到第一电阻器的第二器件电容器，以及可操作地耦合到第二器件电容器的反射镜器件，其中 反射镜装置被布置成提供作为对单个运算放大器的反馈输入的反馈回路，并且被布置成提供电流输出。
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公开(公告)号：US20090143027A1
公开(公告)日：2009-06-04
申请号：US11947240
申请日：2007-11-29
申请人： Ahmad Mirzaei , Alireza Zolfaghari , Hooman Darabi
发明人： Ahmad Mirzaei , Alireza Zolfaghari , Hooman Darabi
IPC分类号： H04B1/40
CPC分类号： H03G1/0029 , H03D7/1441 , H03D7/1458 , H03D7/165 , H03D2200/0025 , H03G1/0088
摘要： An apparatus comprising a plurality of switchable full step mixer unit cells, wherein each switchable full step unit cell is configured to, when the full step transceiver mixer unit cell is turned on, increase the gain experienced by an electronic signal by a full step increment, and wherein the step increment is substantially constant regardless of temperature; and at least one switchable partial step mixer unit cell configured to, when the partial step transceiver mixer unit is turned on, increase the gain experienced by the electronic signal by a predetermined step increment less than that of a full step, and wherein the partial step increment is substantially constant regardless of temperature
摘要翻译： 一种包括多个可切换全步骤混合器单位单元的装置，其中每个可切换全阶单元单元被配置为当全步进收发器混合器单元被接通时，增加电子信号经历的增益全步进增量， 并且其中所述阶梯增量基本上恒定，不管温度如何; 以及至少一个可切换部分步骤混合器单元，其被配置为当所述部分步骤收发器混合器单元被接通时，增加所述电子信号经历的增益小于完整步长的预定步长增量，并且其中所述部分步骤 无论温度如何，增量都是基本恒定的
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8.发明申请ARCHITECTURAL TECHNIQUES FOR ENVELOPE AND PHASE SIGNAL ALIGNMENT IN RF POLAR TRANSMITTERS USING POWER AMPLIFIER FEEDBACK 有权使用功率放大器反馈的RF极性发射器中的信号和相位信号对准的架构技术公开(公告)号：US20090130998A1
公开(公告)日：2009-05-21
申请号：US12356056
申请日：2009-01-19
CPC分类号： H04L27/2003 , H03F1/0211
摘要： In an envelope comparison embodiment, a delay calibrator produces a delay signal based on a comparison of a feedback signal and an envelope component of the transmitted signal. A down-converter produces the feedback signal from an outgoing modulated RF signal based on at least one local oscillation. Envelope detectors in the delay calibrator and the envelope signal path are operably coupled to a summing node that produces a delay error signal based on a temporal difference between the two envelopes. One embodiment includes phase detectors to detect and adjust the zero crossings of the feedback signal and the envelope signal path. As the delay mismatch between the envelope signal path and the phase signal path increases, the power spectrum increases in adjacent communication channels. A mask margin measurement technique measures the power level in an adjacent channel and adjusts the envelope path delay accordingly.
摘要翻译： 在包络比较实施例中，延迟校准器基于反馈信号和发送信号的包络分量的比较产生延迟信号。 下变频器基于至少一个本地振荡产生来自输出调制RF信号的反馈信号。 延迟校准器和包络信号路径中的信封检测器可操作地耦合到求和节点，该求和节点基于两个信封之间的时间差产生延迟误差信号。 一个实施例包括用于检测和调整反馈信号和包络信号路径的过零点的相位检测器。 随着包络信号路径和相位信号路径之间的延迟失配增加，相邻通信信道中的功率谱增加。 掩模余量测量技术测量相邻通道中的功率电平，并相应地调整包络路径延迟。
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公开(公告)号：US07501864B2
公开(公告)日：2009-03-10
申请号：US11835183
申请日：2007-08-07
申请人： Alireza Zolfaghari
发明人： Alireza Zolfaghari
IPC分类号： H03L7/00
CPC分类号： H03K17/22 , H03K2005/00247
摘要： Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal.
摘要翻译： 提供一种用于提供上电复位脉冲的方法和系统。 该系统包括电平检测器，其被配置为当输入信号达到预定电平时接收输入信号并产生至少间接的复位信号。 该系统还包括具有计数特性并被配置为接收复位信号和时钟信号的计数器。 计数器根据计数特性，时钟信号和接收到的复位信号产生延迟信号。
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公开(公告)号：US20070001714A1
公开(公告)日：2007-01-04
申请号：US11169012
申请日：2005-06-29
申请人： Alireza Zolfaghari
发明人： Alireza Zolfaghari
IPC分类号： H03K5/22
CPC分类号： G01R19/16552 , H03K5/082 , H03K17/223
摘要： An input power supply voltage level detection circuit and method are presented. The circuit includes a main detector core and a two-inverter buffer block that can include a first inverter and a second inverter. The circuit receives a voltage input signal and outputs a voltage output signal that is substantially equal to either the voltage input signal or ground, depending on whether the voltage input signal has reached a threshold voltage. The threshold voltage is defined by component characteristics of the main detector core and the two-inverter buffer block. The circuit can receive a hysteresis input signal, tied to the voltage input signal or the ground, that allows the threshold voltage to have a first threshold value when the voltage input signal increases and a second threshold value when the voltage input signal decreases. A power down input signal can also be received that allows the circuit to be powered down.
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