公开(公告)号：US4490629A

公开(公告)日：1984-12-25

申请号：US376903

申请日：1982-05-10

申请人： Allen R. Barlow ,  Corey Petersen

发明人： Allen R. Barlow ,  Corey Petersen

IPC分类号： H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/118 ,  H03F3/42 ,  H03K19/0185 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/0948 ,  H03K19/003 ,  H03K17/10 ,  H03K19/092 ,  H03K19/094

CPC分类号： H01L27/11898 ,  H03F3/42 ,  H03K19/018521 ,  H03K19/09448 ,  H03K19/0948

摘要： A CMOS push-pull output buffer (171) is constructed utilizing a plurality of N channel transistors (74, 75, 76) and a plurality of P channel transistors (71, 72, 73) connected in series. The voltages applied to the gates of the N channel transistors and P channel transistors are selected to divide the high voltage (+V) substantially equally across the P channel transistors, when the P channel transistors are turned off, and substantially evenly divide the high voltage across the N channel transistors, when the N channel transistors are turned off.In another embodiment of this invention, selected ones of the N channel and P channel transistors are formed in order to have a high drain to bulk breakdown voltage.In another embodiment of this invention, a plurality of N channel and a plurality of P channel transistors are connected in series and driven by a single ended control voltage (C.sub.N), thus providing a first stage (101) which drives a second stage (100) having a plurality of P channel transistors and a plurality of N channel transistors (110, 111, 112), which provide the high voltage output voltage.In another embodiment of this invention, the first stage (101) is driven by a single ended control voltage (C.sub.N) and serves to drive a second stage (103) comprising a plurality of N channel transistors (110, 111, 112) and a plurality of bipolar transistors (120, 121), whereby said second stage provides the high voltage output signal.

摘要翻译： 使用串联连接的多个N沟道晶体管（74,75,76）和多个P沟道晶体管（71,72,73）构造CMOS推挽输出缓冲器（171）。 当P沟道晶体管截止时，施加到N沟道晶体管和P沟道晶体管的栅极的电压被选择为在P沟道晶体管中基本上均匀地划分高电压（+ V），并且基本上均匀地划分高电压 跨越N沟道晶体管，当N沟道晶体管截止时。 在本发明的另一个实施例中，形成N沟道和P沟道晶体管中的选定的晶体管以便具有高的漏极到体的击穿电压。 在本发明的另一实施例中，多个N沟道和多个P沟道晶体管串联连接并由单端控制电压（CN）驱动，从而提供驱动第二级（100）的第一级（101） ）具有提供高电压输出电压的多个P沟道晶体管和多个N沟道晶体管（110,111,112）。 在本发明的另一实施例中，第一级（101）由单端控制电压（CN）驱动，并用于驱动包括多个N沟道晶体管（110,111,112）的第二级（103）和 多个双极晶体管（120,121），由此所述第二级提供高电压输出信号。