利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

95 条记录 (耗时 0.025 秒)

    Power Efficient Context-Based Audio Processing
    1.
    发明申请
    Power Efficient Context-Based Audio Processing 有权

    公开(公告)号：US20220030354A1

    公开(公告)日：2022-01-27

    申请号：US17495661

    申请日：2021-10-06

    申请人： Ambiq Micro, Inc.

    发明人： Arpit Shah ,  Scott McLean Hanson ,  Stephen Howard Nease

    IPC分类号： H04R3/04 ,  G06F3/16 ,  G06F3/01 ,  G06F40/205

    摘要： A low power voice processing system that includes a plurality of non-audio sensors, at least one microphone system, and a plurality of audio modules, at least some of which can be configured in selected modes. A context determination module is connected to the plurality of audio modules, and further connected to receive input from the plurality of non-audio sensors and the at least one microphone system. The context determination module acts to determine use context for the voice processing system and at least in part selects mode operation of at least some of the plurality of audio modules.

    Buck Converter With Inductor Sensor
    2.
    发明申请
    Buck Converter With Inductor Sensor 有权

    公开(公告)号：US20210104948A1

    公开(公告)日：2021-04-08

    申请号：US17121593

    申请日：2020-12-14

    申请人： Ambiq Micro, Inc.

    发明人： Ivan Bogue ,  Yousof Mortazavi

    IPC分类号： H02M3/158 ,  H03K17/0814

    摘要： A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.

    Buck Converter With Power Saving Mode
    3.
    发明申请
    Buck Converter With Power Saving Mode 审中-公开

    公开(公告)号：US20200321865A1

    公开(公告)日：2020-10-08

    申请号：US16375345

    申请日：2019-04-04

    申请人： Ambiq Micro, Inc.

    发明人： Ivan Bogue ,  Yanning Lu

    IPC分类号： H02M3/158 ,  H02M1/08 ,  H02M3/157

    摘要： A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.

    Counter/timer array for generation of complex patterns independent of software control
    4.
    发明授权
    Counter/timer array for generation of complex patterns independent of software control 有权

    公开(公告)号：US10416703B2

    公开(公告)日：2019-09-17

    申请号：US15674242

    申请日：2017-08-10

    申请人： Ambiq Micro, Inc.

    发明人： Stephen James Sheafor ,  Donovan Scott Popps

    IPC分类号： G06F1/08 ,  G06F13/42 ,  G06F1/12

    摘要： A system includes an array of counter/timer units that execute a number of timing and pattern generation functions that are selectable by a processor to which the array is coupled. Counter/timer units may receive as inputs the outputs of other counter/timer units, such as for use as a trigger or clock input as instructed by the processor. Counter/timer units may be instructed to execute functions and be coupled to one another by a processor. The processor may then enable the counter/timer units such they subsequently produce complex outputs without additional inputs from the processor. The outputs of the counter/timer units may be used as interrupts to the processor or be used to drive a peripheral device.

    SRAM with multiple power domains
    5.
    发明授权
    SRAM with multiple power domains 有权

    公开(公告)号：US10347328B2

    公开(公告)日：2019-07-09

    申请号：US16049078

    申请日：2018-07-30

    申请人： Ambiq Micro, Inc.

    发明人： Christophe J. Chevallier ,  Scott Hanson

    IPC分类号： G11C7/00 ,  G11C11/419 ,  G11C11/418 ,  G11C5/14

    摘要： An SRAM facility adapted to power an address path using a first developed supply voltage and to power a data path using a second developed supply voltage, the first and second developed power supplies being separate, distinct, and different. The SRAM facility includes a power supply facility or a voltage supply facility adapted to develop the first and second supply voltages.

    SRAM with Error Correction in Retention Mode
    6.
    发明申请
    SRAM with Error Correction in Retention Mode 审中-公开

    公开(公告)号：US20190074056A1

    公开(公告)日：2019-03-07

    申请号：US15982835

    申请日：2018-05-17

    申请人： Ambiq Micro, Inc.

    发明人： Christophe J. Chevallier ,  Stephen James Sheafor

    IPC分类号： G11C11/412 ,  G11C16/34 ,  G11C15/04 ,  G11C11/56

    摘要： A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.