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    Method and apparatus for allowing an interrupt controller on an adapter to control a computer system
    1.
    发明授权
    Method and apparatus for allowing an interrupt controller on an adapter to control a computer system 失效
    允许适配器上的中断控制器控制计算机系统的方法和装置

    公开(公告)号：US5819095A

    公开(公告)日：1998-10-06

    申请号：US769844

    申请日：1996-12-20

    申请人： Louis Bennie Capps, Jr. ,  Son Hung Lam ,  An Xuan Tra

    发明人： Louis Bennie Capps, Jr. ,  Son Hung Lam ,  An Xuan Tra

    IPC分类号： G06F13/24 ,  G06F13/14 ,  G06F9/46

    CPC分类号： G06F13/24

    摘要： A method and apparatus of making a computer system using the peripheral component interconnect (PCI) bus architecture compatible with an Apple computer system are provided. In a preferred embodiment mechanism is used for dedicating interrupt request lines to each of a plurality of input/output (I/O) devices, a mechanism for providing an interrupt request from one of the plurality of I/O devices to a processor, and a mechanism for disabling an interrupt controller on the motherboard of the system (or onboard interrupt controller) so as to allow an interrupt controller residing on an Apple adapter to control the system. The interrupt controller on the Apple adapter contains an input for each of the various I/O adapters attached to the computer system and also provides a request line to the processor.

    摘要翻译： 提供了使用与Apple计算机系统兼容的外围组件互连（PCI）总线架构来制造计算机系统的方法和装置。 在优选实施例中，机制用于将中断请求线专用于多个输入/输出（I / O）设备中的每一个，用于将多个I / O设备之一的中断请求提供给处理器的机制，以及 一种用于禁用系统（或板载中断控制器）主板上的中断控制器的机制，以允许驻留在Apple适配器上的中断控制器来控制系统。 Apple适配器上的中断控制器包含连接到计算机系统的各种I / O适配器的输入，并为处理器提供请求线。

    Adapter with an onboard interrupt controller for controlling a computer system
    2.
    发明授权
    Adapter with an onboard interrupt controller for controlling a computer system 失效
    具有用于控制计算机系统的板载中断控制器的适配器

    公开(公告)号：US5787290A

    公开(公告)日：1998-07-28

    申请号：US769843

    申请日：1996-12-20

    申请人： Louis Bennie Capps, Jr. ,  Son Hung Lam ,  An Xuan Tra

    发明人： Louis Bennie Capps, Jr. ,  Son Hung Lam ,  An Xuan Tra

    IPC分类号： G06F13/24 ,  G06F13/14 ,  G06F9/46

    CPC分类号： G06F13/24

    摘要： A CHRP compliant Apple adapter is provided. The adapter comprises an onboard interrupt controller to control a peripheral component interconnect (PCI) based computer system. The adapter also comprises a mechanism for disabling a pre-existing system interrupt controller. The onboard interrupt controller contains an interrupt request input for each of a plurality of I/O devices attached to the computer system and also provides an interrupt request to a processor.

    摘要翻译： 提供符合CHRP标准的Apple适配器。 适配器包括板载中断控制器，用于控制基于外围组件互连（PCI）的计算机系统。 适配器还包括用于禁用预先存在的系统中断控制器的机构。 板载中断控制器包含连接到计算机系统的多个I / O设备中的每一个的中断请求输入，并且还向处理器提供中断请求。

    Method and apparatus of programming FPGA devices through ASIC devices
    3.
    发明授权
    Method and apparatus of programming FPGA devices through ASIC devices 失效
    通过ASIC器件编程FPGA器件的方法和设备

    公开(公告)号：US5867037A

    公开(公告)日：1999-02-02

    申请号：US736303

    申请日：1996-10-24

    申请人： Louis Bennie Capps, Jr. ,  Richard Nicholas Iachetta, Jr. ,  An Xuan Tra

    发明人： Louis Bennie Capps, Jr. ,  Richard Nicholas Iachetta, Jr. ,  An Xuan Tra

    IPC分类号： G06F17/50 ,  H03K19/173

    CPC分类号： G06F17/5054

    摘要： A method and apparatus for receiving and transmitting programming data through an application specific integrated circuit is provided. In a first embodiment, the application specific integrated circuit comprises a main circuit, at least two input/output (I/O) mechanisms connected to the main circuit for transferring data into and out of the main circuit and a mechanism for receiving and transmitting the programming data. The mechanism for transmitting the programming data includes a tri-state buffer that is activated by a programming enable signal. In a second embodiment, the input and output of the buffer are multiplexed with the two I/O mechanisms connected to the main circuit.

    摘要翻译： 提供了一种通过专用集成电路接收和发送编程数据的方法和装置。 在第一实施例中，专用集成电路包括主电路，连接到主电路的用于将数据传入和传出主电路的至少两个输入/输出（I / O）机构，以及用于接收和发送 编程数据。 用于发送编程数据的机制包括由编程使能信号激活的三态缓冲器。 在第二实施例中，缓冲器的输入和输出与连接到主电路的两个I / O机构复用。