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1.发明授权Method and apparatus for automatic frequency and voltage selection for microprocessors 失效用于微处理器自动频率和电压选择的方法和装置
公开(公告)号：US5764529A
公开(公告)日：1998-06-09
申请号：US773544
申请日：1996-12-23
CPC分类号： G06F1/08 , G06F1/26 , H01L2223/5444
摘要： A method and apparatus for providing automatic frequency and voltage selection for microprocessors in a computer system. Microprocessor identification (ID) bits are burned into a microprocessor during manufacture to specify the correct bus frequency and core voltage. A clock generator and voltage regulator are provided to receive and interpret the ID bits and provide the correct frequency and voltage.
摘要翻译： 一种用于在计算机系统中为微处理器提供自动频率和电压选择的方法和装置。 微处理器识别（ID）位在制造过程中刻录到微处理器中，以指定正确的总线频率和核心电压。 提供时钟发生器和电压调节器来接收和解释ID位并提供正确的频率和电压。
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2.发明授权Method and apparatus for allowing an interrupt controller on an adapter to control a computer system 失效允许适配器上的中断控制器控制计算机系统的方法和装置
公开(公告)号：US5819095A
公开(公告)日：1998-10-06
申请号：US769844
申请日：1996-12-20
CPC分类号： G06F13/24
摘要： A method and apparatus of making a computer system using the peripheral component interconnect (PCI) bus architecture compatible with an Apple computer system are provided. In a preferred embodiment mechanism is used for dedicating interrupt request lines to each of a plurality of input/output (I/O) devices, a mechanism for providing an interrupt request from one of the plurality of I/O devices to a processor, and a mechanism for disabling an interrupt controller on the motherboard of the system (or onboard interrupt controller) so as to allow an interrupt controller residing on an Apple adapter to control the system. The interrupt controller on the Apple adapter contains an input for each of the various I/O adapters attached to the computer system and also provides a request line to the processor.
摘要翻译： 提供了使用与Apple计算机系统兼容的外围组件互连（PCI）总线架构来制造计算机系统的方法和装置。 在优选实施例中，机制用于将中断请求线专用于多个输入/输出（I / O）设备中的每一个，用于将多个I / O设备之一的中断请求提供给处理器的机制，以及 一种用于禁用系统（或板载中断控制器）主板上的中断控制器的机制，以允许驻留在Apple适配器上的中断控制器来控制系统。 Apple适配器上的中断控制器包含连接到计算机系统的各种I / O适配器的输入，并为处理器提供请求线。
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3.发明授权Adapter with an onboard interrupt controller for controlling a computer system 失效具有用于控制计算机系统的板载中断控制器的适配器
公开(公告)号：US5787290A
公开(公告)日：1998-07-28
申请号：US769843
申请日：1996-12-20
CPC分类号： G06F13/24
摘要： A CHRP compliant Apple adapter is provided. The adapter comprises an onboard interrupt controller to control a peripheral component interconnect (PCI) based computer system. The adapter also comprises a mechanism for disabling a pre-existing system interrupt controller. The onboard interrupt controller contains an interrupt request input for each of a plurality of I/O devices attached to the computer system and also provides an interrupt request to a processor.
摘要翻译： 提供符合CHRP标准的Apple适配器。 适配器包括板载中断控制器，用于控制基于外围组件互连（PCI）的计算机系统。 适配器还包括用于禁用预先存在的系统中断控制器的机构。 板载中断控制器包含连接到计算机系统的多个I / O设备中的每一个的中断请求输入，并且还向处理器提供中断请求。
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4.发明授权
公开(公告)号：US5867037A
公开(公告)日：1999-02-02
申请号：US736303
申请日：1996-10-24
IPC分类号： G06F17/50 , H03K19/173
CPC分类号： G06F17/5054
摘要： A method and apparatus for receiving and transmitting programming data through an application specific integrated circuit is provided. In a first embodiment, the application specific integrated circuit comprises a main circuit, at least two input/output (I/O) mechanisms connected to the main circuit for transferring data into and out of the main circuit and a mechanism for receiving and transmitting the programming data. The mechanism for transmitting the programming data includes a tri-state buffer that is activated by a programming enable signal. In a second embodiment, the input and output of the buffer are multiplexed with the two I/O mechanisms connected to the main circuit.
摘要翻译： 提供了一种通过专用集成电路接收和发送编程数据的方法和装置。 在第一实施例中，专用集成电路包括主电路，连接到主电路的用于将数据传入和传出主电路的至少两个输入/输出（I / O）机构，以及用于接收和发送 编程数据。 用于发送编程数据的机制包括由编程使能信号激活的三态缓冲器。 在第二实施例中，缓冲器的输入和输出与连接到主电路的两个I / O机构复用。
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5.发明授权Parallelizing single threaded programs by performing look ahead operation on the single threaded program to identify plurality of instruction threads prior to execution 有权通过对单线程程序执行前瞻性操作来在执行之前识别多条指令线程来并行化单线程程序公开(公告)号：US08495636B2
公开(公告)日：2013-07-23
申请号：US11959906
申请日：2007-12-19
IPC分类号： G06F9/46
CPC分类号： G06F9/5066
摘要： A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.
摘要翻译： 一种用于在多核处理器内推测地执行单线程程序的方法和装置，其包括识别所述多核处理器内的空闲核心，对所述单线程指令执行向前操作以识别所述单线程指令内的推测指令， 并分配空闲核心以执行推测性指令。
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公开(公告)号：US08379847B2
公开(公告)日：2013-02-19
申请号：US12828080
申请日：2010-06-30
CPC分类号： H04L9/06 , H04L9/0618 , H04L2209/125
摘要： Secure communication of data between devices includes encrypting unencrypted data at a first device by reordering unencrypted bits provided in parallel on a device bus, including data and control bits, from an unencrypted order to form encrypted data including a plurality of encrypted bits in parallel in an encrypted order defined by a key. The encrypted data may be transmitted to another device where the encrypted data is decrypted by using the key to order the encrypted bits to restore the unencrypted order thereby to reform the unencrypted data.
摘要翻译： 设备之间的数据的安全通信包括通过从未加密的顺序重新排序设备总线（包括数据和控制位）并行提供的未加密比特来在第一设备处对未加密的数据进行加密，以形成包括多个加密比特的加密数据 由密钥定义的加密顺序。 加密数据可以通过使用密钥来对加密数据进行解密的另一设备发送到另一个设备，以对加密的比特进行命令以恢复未加密的顺序，从而改变未加密的数据。
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公开(公告)号：US07930129B2
公开(公告)日：2011-04-19
申请号：US12114032
申请日：2008-05-02
CPC分类号： G01R31/2868
摘要： A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
摘要翻译： 提供计算机实现的方法，数据处理系统和计算机可用代码用于多处理器的老化测试。 过程识别与多处理器相关联的多个处理器核心的功率管理数据集。 该过程基于电源管理数据集选择多个处理器核中的一个或多个来形成选定的一组处理器核。 该过程在所选的一组处理器核心上启动老化测试。 响应于确定多个处理器核心中的所有处理器核心未被选择，该过程重复上述选择和启动步骤，直到所有处理器核心已被选择为止。
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8.发明授权System and method to optimize multi-core microprocessor performance using voltage offsets 失效使用电压补偿优化多核微处理器性能的系统和方法公开(公告)号：US07721119B2
公开(公告)日：2010-05-18
申请号：US11466891
申请日：2006-08-24
申请人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
发明人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
摘要翻译： 提出了使用电压偏移来优化多核微处理器性能的系统和方法。 多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。 反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。 结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。 电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。
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9.发明授权Method and apparatus for controlling heat generation in a multi-core processor 有权用于控制多核处理器中的发热的方法和装置公开(公告)号：US07617403B2
公开(公告)日：2009-11-10
申请号：US11459988
申请日：2006-07-26
CPC分类号： G06F1/206
摘要： The disclosed methodology and apparatus may reduce heat generation in a multi-core processor. In one embodiment, a multi-core processor cycles selected processor cores off in a predetermined pattern across the processor die over time to reduce the average heat generation by the processor. The disclosed multi-core processor may reduce or avoid undesirable hot spots that impact processor life.
摘要翻译： 所公开的方法和装置可以减少多核处理器中的发热。 在一个实施例中，多核处理器随着时间跨越处理器管芯以预定模式关闭所选择的处理器核，以减少处理器的平均发热量。 所公开的多核处理器可以减少或避免影响处理器寿命的不期望的热点。
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10.发明授权Structure for an apparatus for monitoring and controlling heat generation in a multi-core processor 有权用于在多核处理器中监测和控制发热的装置的结构公开(公告)号：US08214660B2
公开(公告)日：2012-07-03
申请号：US12347947
申请日：2008-12-31
CPC分类号： G06F1/206
摘要： A design structure for a processor may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may control heat generation in a multi-core processor. The design structure may specify that each processor core includes a temperature sensor that reports temperature information to a processor controller. The design structure may also specify that if a particular processor core exceeds a predetermined temperature, the processor controller disables that processor core to allow that processor core to cool. The design structure may also specify that the processor controller enables the previously disabled processor core when the previously disabled processor core cools sufficiently to a normal operating temperature. In this manner, a multi-core processor may avoid undesirable hot spots that impact processor life.
摘要翻译： 用于处理器的设计结构可以体现在用于设计，制造或测试处理器集成电路的机器可读介质中。 该设计结构可以控制多核处理器中的发热。 设计结构可以指定每个处理器核心包括向处理器控制器报告温度信息的温度传感器。 该设计结构还可以指定如果特定处理器核心超过预定温度，则处理器控制器禁止该处理器核心使该处理器核心冷却。 设计结构还可以指定当先前禁用的处理器核心充分冷却至正常工作温度时，处理器控制器启用先前禁用的处理器核心。 以这种方式，多核处理器可以避免影响处理器寿命的不期望的热点。
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