公开(公告)号：US20130168767A1

公开(公告)日：2013-07-04

申请号：US13342189

申请日：2012-01-02

Applicant: An-Hung Lin ,  Hong-Ze Lin ,  Bo-Jui Huang ,  Wei-Shan Liao ,  Ting-Zhou Yan ,  Kun-Yi Chou ,  Chun-Wei Chen ,  Ming-Yong Jian

Inventor： An-Hung Lin ,  Hong-Ze Lin ,  Bo-Jui Huang ,  Wei-Shan Liao ,  Ting-Zhou Yan ,  Kun-Yi Chou ,  Chun-Wei Chen ,  Ming-Yong Jian

IPC: H01L27/06 ,  H01L29/78

CPC classification number: H01L27/0727 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/782

Abstract: The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region.

Abstract translation: 本发明提供了包括第一掺杂区，第二掺杂区，第三掺杂区，栅极结构和接触金属的横向扩散金属氧化物半导体器件。 第一掺杂区域和第三掺杂区域具有第一导电类型，并且第二掺杂区域具有第二导电类型。 具有跑道形状布局的第二掺杂区域设置在第一掺杂区域中并且具有长轴。 第三掺杂区域设置在第二掺杂区域中。 栅极结构设置在第一掺杂区域和第二掺杂区域的第三掺杂区域的一侧。 接触金属设置在沿着长轴延伸出的第二掺杂区域的一侧上的第一掺杂区域上，并与第一掺杂区域接触。

公开(公告)号：US08466019B2

公开(公告)日：2013-06-18

申请号：US13267846

申请日：2011-10-06

Applicant: Chu-Feng Chen ,  Chung-Ren Lao ,  Pai-Chun Kuo ,  Chien-Hsien Song ,  Hua-Chun Chiue ,  An-Hung Lin

Inventor： Chu-Feng Chen ,  Chung-Ren Lao ,  Pai-Chun Kuo ,  Chien-Hsien Song ,  Hua-Chun Chiue ,  An-Hung Lin

IPC: H01L29/72

CPC classification number: H01L21/8249 ,  H01L27/0623 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.

Abstract translation: 描述半导体器件制造方法。 半导体器件制造方法包括在衬底上形成外延层，其中外延层与衬底具有相同的导电类型。 在外延层中形成具有与外延层不同的导电类型的第一掺杂区。 执行退火处理以在第一掺杂区域中扩散掺杂剂。 在第一掺杂区域中形成第二掺杂区域和相邻的第三掺杂区域。 第二掺杂区域是与第一掺杂区域不同的导电类型，并且第三掺杂区域是与第一掺杂区域相同的导电类型。 在覆盖第二和第三掺杂区域的一部分的外延层上形成栅极结构。

公开(公告)号：US20130126968A1

公开(公告)日：2013-05-23

申请号：US13299446

申请日：2011-11-18

Applicant: An-Hung LIN ,  Hong-Ze Lin ,  Bo-Jui Huang ,  Wei-Shan Liao ,  Ting-Zhou Yan ,  Wei-Chun Chang ,  Chun-Yao Lee ,  Kun-Yi Chou

Inventor： An-Hung LIN ,  Hong-Ze Lin ,  Bo-Jui Huang ,  Wei-Shan Liao ,  Ting-Zhou Yan ,  Wei-Chun Chang ,  Chun-Yao Lee ,  Kun-Yi Chou

IPC: H01L29/78

CPC classification number: H01L29/0696 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7816 ,  H01L29/7835

Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.

Abstract translation: 提供高压半导体器件。 在衬底中形成第一极性掩埋层。 第一高电压第二极性阱区位于第一极性掩埋层的上方。 第二极性基极区域设置在第一高电压第二极性阱区域内。 源极区域设置在第二极性基极区域内。 高电压深的第一极性极区位于第一极性埋层之上，紧邻第一高电压第二极性阱区。 第一极性漂移区域设置在高电压深第一极性阱区域内。 栅极结构设置在衬底上。 第二高电压第二极性阱区域位于第一极性掩埋层上方并且紧邻高电压深第一极性阱区域。 深第一极性阱区域位于第一极性掩埋层上并且紧邻第二高电压第二极性阱区域。

公开(公告)号：US20120161699A1

公开(公告)日：2012-06-28

申请号：US13028219

申请日：2011-02-16

Applicant: Wen-Shu Chiang ,  Chin-Pin Chien ,  An-Hung Lin

Inventor： Wen-Shu Chiang ,  Chin-Pin Chien ,  An-Hung Lin

IPC: H02J7/00

CPC classification number: H02J7/0004 ,  B60L11/1816 ,  B60L11/1824 ,  B60L11/1844 ,  B60L11/1846 ,  B60L2230/40 ,  B60L2240/70 ,  Y02E60/721 ,  Y02T10/7005 ,  Y02T10/7088 ,  Y02T10/7291 ,  Y02T90/121 ,  Y02T90/128 ,  Y02T90/14 ,  Y02T90/16 ,  Y02T90/163 ,  Y02T90/168 ,  Y02T90/169 ,  Y04S10/126 ,  Y04S30/12 ,  Y04S30/14

Abstract: An interactive charging management system and a method thereof are provided. The method is applicable to a plurality of electric vehicles, and which includes dynamically adjusting usable power information respectively provided by a plurality of charging posts respectively corresponding to and coupled to the electric vehicles according to demand power information of the respective electric vehicles; and making the charging posts non-uniformly provide a plurality of charging powers to the respective electric vehicles according to the adjusted usable power information.

Abstract translation: 提供了交互式计费管理系统及其方法。 该方法适用于多个电动车辆，其包括根据各电动车辆的需求功率信息动态调整分别对应于电动车辆并耦合到电动车辆的多个充电站分别提供的可用功率信息; 并且根据调整后的可用功率信息使充电柱不均匀地向各电动车辆提供多个充电功率。

公开(公告)号：US08058121B2

公开(公告)日：2011-11-15

申请号：US12494188

申请日：2009-06-29

Applicant: Chu-Feng Chen ,  Chung-Ren Lao ,  Pai-Chun Kuo ,  Chien-Hsien Song ,  Hua-Chun Chiue ,  An-Hung Lin

Inventor： Chu-Feng Chen ,  Chung-Ren Lao ,  Pai-Chun Kuo ,  Chien-Hsien Song ,  Hua-Chun Chiue ,  An-Hung Lin

IPC: H01L29/72

CPC classification number: H01L21/8249 ,  H01L27/0623 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.

Abstract translation: 描述半导体器件制造方法。 半导体器件制造方法包括在衬底上形成外延层，其中外延层与衬底具有相同的导电类型。 在外延层中形成具有与外延层不同的导电类型的第一掺杂区。 执行退火处理以在第一掺杂区域中扩散掺杂剂。 在第一掺杂区域中形成第二掺杂区域和相邻的第三掺杂区域。 第二掺杂区域是与第一掺杂区域不同的导电类型，并且第三掺杂区域是与第一掺杂区域相同的导电类型。 在覆盖第二和第三掺杂区域的一部分的外延层上形成栅极结构。

公开(公告)号：US08587058B2

公开(公告)日：2013-11-19

申请号：US13342189

申请日：2012-01-02

Applicant: An-Hung Lin ,  Hong-Ze Lin ,  Bo-Jui Huang ,  Wei-Shan Liao ,  Ting-Zhou Yan ,  Kun-Yi Chou ,  Chun-Wei Chen ,  Ming-Yong Jian

Inventor： An-Hung Lin ,  Hong-Ze Lin ,  Bo-Jui Huang ,  Wei-Shan Liao ,  Ting-Zhou Yan ,  Kun-Yi Chou ,  Chun-Wei Chen ,  Ming-Yong Jian

IPC: H01L29/66

CPC classification number: H01L27/0727 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/782

Abstract: The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region.

Abstract translation: 本发明提供了包括第一掺杂区，第二掺杂区，第三掺杂区，栅极结构和接触金属的横向扩散金属氧化物半导体器件。 第一掺杂区域和第三掺杂区域具有第一导电类型，并且第二掺杂区域具有第二导电类型。 具有跑道形状布局的第二掺杂区域设置在第一掺杂区域中并且具有长轴。 第三掺杂区域设置在第二掺杂区域中。 栅极结构设置在第一掺杂区域和第二掺杂区域的第三掺杂区域的一侧。 接触金属设置在沿着长轴延伸出的第二掺杂区域的一侧上的第一掺杂区域上，并与第一掺杂区域接触。

公开(公告)号：US08508187B2

公开(公告)日：2013-08-13

申请号：US13028219

申请日：2011-02-16

Applicant: Wen-Shu Chiang ,  Chin-Pin Chien ,  An-Hung Lin

Inventor： Wen-Shu Chiang ,  Chin-Pin Chien ,  An-Hung Lin

IPC: H02J7/00 ,  B60K6/20

CPC classification number: H02J7/0004 ,  B60L11/1816 ,  B60L11/1824 ,  B60L11/1844 ,  B60L11/1846 ,  B60L2230/40 ,  B60L2240/70 ,  Y02E60/721 ,  Y02T10/7005 ,  Y02T10/7088 ,  Y02T10/7291 ,  Y02T90/121 ,  Y02T90/128 ,  Y02T90/14 ,  Y02T90/16 ,  Y02T90/163 ,  Y02T90/168 ,  Y02T90/169 ,  Y04S10/126 ,  Y04S30/12 ,  Y04S30/14

Abstract: An interactive charging management system and a method thereof are provided. The method is applicable to a plurality of electric vehicles, and which includes dynamically adjusting usable power information respectively provided by a plurality of charging posts respectively corresponding to and coupled to the electric vehicles according to demand power information of the respective electric vehicles; and making the charging posts non-uniformly provide a plurality of charging powers to the respective electric vehicles according to the adjusted usable power information.

Abstract translation: 提供了交互式计费管理系统及其方法。 该方法适用于多个电动车辆，其包括根据各电动车辆的需求功率信息动态调整分别对应于电动车辆并耦合到电动车辆的多个充电站分别提供的可用功率信息; 并且根据调整后的可用功率信息使充电柱不均匀地向各电动车辆提供多个充电功率。

公开(公告)号：US08482063B2

公开(公告)日：2013-07-09

申请号：US13299446

申请日：2011-11-18

Applicant: An-Hung Lin ,  Hong-Ze Lin ,  Bo-Jui Huang ,  Wei-Shan Liao ,  Ting-Zhou Yan ,  Wei-Chun Chang ,  Chun-Yao Lee ,  Kun-Yi Chou

Inventor： An-Hung Lin ,  Hong-Ze Lin ,  Bo-Jui Huang ,  Wei-Shan Liao ,  Ting-Zhou Yan ,  Wei-Chun Chang ,  Chun-Yao Lee ,  Kun-Yi Chou

IPC: H01L29/66

CPC classification number: H01L29/0696 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7816 ,  H01L29/7835

Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.

Abstract translation: 提供高压半导体器件。 在衬底中形成第一极性掩埋层。 第一高电压第二极性阱区位于第一极性掩埋层的上方。 第二极性基极区域设置在第一高电压第二极性阱区域内。 源极区域设置在第二极性基极区域内。 高电压深的第一极性极区位于第一极性埋层之上，紧邻第一高电压第二极性阱区。 第一极性漂移区域设置在高电压深第一极性阱区域内。 栅极结构设置在衬底上。 第二高电压第二极性阱区域位于第一极性掩埋层上方并且紧邻高电压深第一极性阱区域。 深第一极性阱区域位于第一极性掩埋层上并且紧邻第二高电压第二极性阱区域。

公开(公告)号：US20120286359A1

公开(公告)日：2012-11-15

申请号：US13105912

申请日：2011-05-12

Applicant: An-Hung Lin ,  Hong-Ze Lin ,  Bo-Jui Huang ,  Wei-Shan Liao ,  Ting-Zhou Yan ,  Kun-Yi Chou ,  Chun-Wei Chen

Inventor： An-Hung Lin ,  Hong-Ze Lin ,  Bo-Jui Huang ,  Wei-Shan Liao ,  Ting-Zhou Yan ,  Kun-Yi Chou ,  Chun-Wei Chen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7824 ,  H01L29/7835

Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.

Abstract translation: 横向扩散的金属氧化物半导体器件（LDMOS）包括衬底，第一深阱，至少场氧化物层，栅极，第二深阱，第一掺杂区，漏极和公共源。 衬底具有第一导电类型的第一深阱。 栅极设置在衬底上并覆盖场氧化物层的一部分。 具有第二导电类型的第二深阱设置在衬底中并且紧邻第一深孔。 具有第二导电类型的第一掺杂区域设置在第二深阱中。 第一掺杂剂区域的掺杂浓度高于第二深阱的掺杂浓度。

公开(公告)号：US20120025308A1

公开(公告)日：2012-02-02

申请号：US13267846

申请日：2011-10-06

Applicant: Chu-Feng Chen ,  Chung-Ren Lao ,  Pai-Chun Kuo ,  Chien-Hsien Song ,  Hua-Chun Chiue ,  An-Hung Lin

Inventor： Chu-Feng Chen ,  Chung-Ren Lao ,  Pai-Chun Kuo ,  Chien-Hsien Song ,  Hua-Chun Chiue ,  An-Hung Lin

IPC: H01L29/78

CPC classification number: H01L21/8249 ,  H01L27/0623 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.

Abstract translation: 描述半导体器件制造方法。 半导体器件制造方法包括在衬底上形成外延层，其中外延层与衬底具有相同的导电类型。 在外延层中形成具有与外延层不同的导电类型的第一掺杂区。 执行退火处理以在第一掺杂区域中扩散掺杂剂。 在第一掺杂区域中形成第二掺杂区域和相邻的第三掺杂区域。 第二掺杂区域是与第一掺杂区域不同的导电类型，并且第三掺杂区域是与第一掺杂区域相同的导电类型。 在覆盖第二和第三掺杂区域的一部分的外延层上形成栅极结构。