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1.发明授权公开(公告)号：US08373460B2
公开(公告)日：2013-02-12
申请号：US13072818
申请日：2011-03-28
申请人： Anand K. Sinha , Sanjay K. Wadhwa
发明人： Anand K. Sinha , Sanjay K. Wadhwa
IPC分类号： H03L7/06
CPC分类号： H03L7/089
摘要： A dual loop PLL for generating an oscillator signal initially operates in a digital loop to achieve a frequency lock between an input reference signal and a feedback signal and then the PLL operates in an analog loop to achieve a phase lock. After attaining the phase lock, the analog loop is used to maintain the phase lock across frequency and phase variation due to changes in temperature and supply.
摘要翻译： 用于产生振荡器信号的双环PLL最初在数字环路中工作，以实现输入参考信号和反馈信号之间的频率锁定，然后PLL以模拟环路操作以实现锁相。 达到锁相后，由于温度和电源的变化，模拟环路用于保持频率和相位变化的相位锁定。
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公开(公告)号：US20120176169A1
公开(公告)日：2012-07-12
申请号：US13004043
申请日：2011-01-11
申请人： Anand K. Sinha , Sanjay K. Wadhwa
发明人： Anand K. Sinha , Sanjay K. Wadhwa
IPC分类号： H03L7/08
CPC分类号： H03L7/1075 , H03L2207/50
摘要： A method to operate a digital phase locked loop (DPLL) in which the DPLL includes a phase-frequency detector that compares the frequency of a reference signal with a feedback signal to generate an error signal. The error signal is used to generate first and second control words. Binary current control word bits and thermometric current control word bits are generated using the first and second control words, respectively. A binary controller switches a first set of binary current sources prior to a frequency lock being achieved using the binary current control word bits and the thermometric current control word bits are held at a predetermined value. After achieving the frequency lock, the binary current sources are fixed and then a thermometric controller switches a second set of thermometric current sources using the thermometric current control word bits. Operating the DPLL using the binary controller before the frequency lock and the thermometric controller after the frequency lock reduces switching noise and achieves stable loop dynamics.
摘要翻译： 一种操作数字锁相环（DPLL）的方法，其中DPLL包括将参考信号的频率与反馈信号进行比较以产生误差信号的相位频率检测器。 误差信号用于产生第一和第二控制字。 分别使用第一和第二控制字产生二进制电流控制字位和测温电流控制字位。 二进制控制器在使用二进制电流控制字位实现频率锁定之前切换第一组二进制电流源，并且将测温电流控制字位保持在预定值。 在实现频率锁定之后，二进制电流源是固定的，然后温度控制器使用温度计电流控制字位来切换第二组测温电流源。 频率锁定之前使用二进制控制器操作DPLL，频率锁定后的温度控制器可以降低开关噪声并实现稳定的环路动态。
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3.发明申请公开(公告)号：US20120249198A1
公开(公告)日：2012-10-04
申请号：US13072818
申请日：2011-03-28
申请人： Anand K. Sinha , Sanjay K. Wadhwa
发明人： Anand K. Sinha , Sanjay K. Wadhwa
IPC分类号： H03L7/08
CPC分类号： H03L7/089
摘要： A dual loop PLL for generating an oscillator signal initially operates in a digital loop to achieve a frequency lock between an input reference signal and a feedback signal and then the PLL operates in an analog loop to achieve a phase lock. After attaining the phase lock, the analog loop is used to maintain the phase lock across frequency and phase variation due to changes in temperature and supply.
摘要翻译： 用于产生振荡器信号的双环PLL最初在数字环路中工作，以实现输入参考信号和反馈信号之间的频率锁定，然后PLL以模拟环路操作以实现锁相。 达到锁相后，由于温度和电源的变化，模拟环路用于保持频率和相位变化的相位锁定。
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公开(公告)号：US20120133405A1
公开(公告)日：2012-05-31
申请号：US12954625
申请日：2010-11-25
IPC分类号： H03L7/06
摘要： A start-up circuit for a PLL includes a phase-frequency detector (PFD), one or more logic gates, a flip-flop and a false detection circuit. The false detection circuit includes a set of series connected flip-flops. The PFD receives a reference signal and a feedback signal. The PFD compares the frequency of a reference signal with that of a feedback signal. If the frequency of the reference signal is greater than the frequency of the feedback signal then a start-up signal is generated and transmitted to the PLL. The PLL increases the frequency of the feedback signal until it is greater than the frequency of the reference signal. The generation of the start-up signal is halted when the frequency of the feedback signal is greater than the frequency of the reference signal.
摘要翻译： PLL的启动电路包括相位频率检测器（PFD），一个或多个逻辑门，触发器和错误检测电路。 错误检测电路包括一组串联的触发器。 PFD接收参考信号和反馈信号。 PFD将参考信号的频率与反馈信号的频率进行比较。 如果参考信号的频率大于反馈信号的频率，则产生启动信号并发送到PLL。 PLL增加反馈信号的频率，直到其大于参考信号的频率。 当反馈信号的频率大于参考信号的频率时，启动信号的产生被停止。
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公开(公告)号：US08354866B2
公开(公告)日：2013-01-15
申请号：US12954625
申请日：2010-11-25
IPC分类号： H03L7/00
摘要： A start-up circuit for a PLL includes a phase-frequency detector (PFD), one or more logic gates, a flip-flop and a false detection circuit. The false detection circuit includes a set of series connected flip-flops. The PFD receives a reference signal and a feedback signal. The PFD compares the frequency of a reference signal with that of a feedback signal. If the frequency of the reference signal is greater than the frequency of the feedback signal then a start-up signal is generated and transmitted to the PLL. The PLL increases the frequency of the feedback signal until it is greater than the frequency of the reference signal. The generation of the start-up signal is halted when the frequency of the feedback signal is greater than the frequency of the reference signal.
摘要翻译： PLL的启动电路包括相位频率检测器（PFD），一个或多个逻辑门，触发器和错误检测电路。 错误检测电路包括一组串联的触发器。 PFD接收参考信号和反馈信号。 PFD将参考信号的频率与反馈信号的频率进行比较。 如果参考信号的频率大于反馈信号的频率，则产生启动信号并发送到PLL。 PLL增加反馈信号的频率，直到其大于参考信号的频率。 当反馈信号的频率大于参考信号的频率时，启动信号的产生被停止。
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公开(公告)号：US08253458B2
公开(公告)日：2012-08-28
申请号：US13004043
申请日：2011-01-11
申请人： Anand K. Sinha , Sanjay K. Wadhwa
发明人： Anand K. Sinha , Sanjay K. Wadhwa
IPC分类号： H03L7/06
CPC分类号： H03L7/1075 , H03L2207/50
摘要： A method to operate a digital phase locked loop (DPLL) in which the DPLL includes a phase-frequency detector that compares the frequency of a reference signal with a feedback signal to generate an error signal. The error signal is used to generate first and second control words. Binary current control word bits and thermometric current control word bits are generated using the first and second control words, respectively. A binary controller switches a first set of binary current sources prior to a frequency lock being achieved using the binary current control word bits and the thermometric current control word bits are held at a predetermined value. After achieving the frequency lock, the binary current sources are fixed and then a thermometric controller switches a second set of thermometric current sources using the thermometric current control word bits. Operating the DPLL using the binary controller before the frequency lock and the thermometric controller after the frequency lock reduces switching noise and achieves stable loop dynamics.
摘要翻译： 一种操作数字锁相环（DPLL）的方法，其中DPLL包括将参考信号的频率与反馈信号进行比较以产生误差信号的相位频率检测器。 误差信号用于产生第一和第二控制字。 分别使用第一和第二控制字产生二进制电流控制字位和测温电流控制字位。 二进制控制器在使用二进制电流控制字位实现频率锁定之前切换第一组二进制电流源，并且将测温电流控制字位保持在预定值。 在实现频率锁定之后，二进制电流源是固定的，然后温度控制器使用温度计电流控制字位来切换第二组测温电流源。 频率锁定之前使用二进制控制器操作DPLL，频率锁定后的温度控制器可以降低开关噪声并实现稳定的环路动态。
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