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公开(公告)号：US08988114B2
公开(公告)日：2015-03-24
申请号：US13681956
申请日：2012-11-20
CPC分类号： G05F3/02 , G01R19/16552 , G06F1/28
摘要： Systems and methods for low-power voltage tamper detection are described. In some embodiments, an integrated circuit may include source-follower circuitry configured to produce a scaled down supply voltage. The integrated circuit may also include undervoltage detection circuitry coupled to the source-follower circuitry, the undervoltage detection circuitry configured to output a first signal having a first logic value if the scaled down supply voltage is greater than a low threshold voltage or a second logic value if the scaled down supply voltage is smaller than the low threshold voltage. Additionally or alternatively, the integrated circuit may include overvoltage detection circuitry coupled to the source-follower circuitry, the overvoltage detection circuitry configured to output a second signal having the first logic value if the scaled down supply voltage is smaller than a high threshold voltage or the second logic value if the scaled down supply voltage is greater than the high threshold voltage.
摘要翻译： 描述了用于低功率电压篡改检测的系统和方法。 在一些实施例中，集成电路可以包括被配置为产生按比例缩小的电源电压的源跟随器电路。 集成电路还可以包括耦合到源跟随器电路的欠压检测电路，欠压检测电路被配置为如果按比例缩小的电源电压大于低阈值电压或第二逻辑值，则输出具有第一逻辑值的第一信号 如果按比例缩小的电源电压小于低阈值电压。 附加地或替代地，集成电路可以包括耦合到源极跟随器电路的过电压检测电路，该过电压检测电路被配置为如果按比例缩小的电源电压小于高阈值电压，则输出具有第一逻辑值的第二信号，或者 如果按比例缩小的电源电压大于高阈值电压，则为第二逻辑值。
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公开(公告)号：US07009424B2
公开(公告)日：2006-03-07
申请号：US10865269
申请日：2004-06-10
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/356008
摘要： A level shifter that shifts a low supply voltage input signal to a higher supply voltage output signal includes a first unit and a second unit. The first unit is connected to a high power supply voltage source and receives the input signal. The first unit acts as a startup circuit such that when the level shifter is switched on, the first unit discharges an output node if the input signal is a logic low, and when the input signal is a logic high, the first unit charges a control node to the voltage of the input signal. The second unit is connected to the first unit and the high power supply voltage source, and also receives the input signal. The second unit shifts the input signal to the higher supply voltage output signal. The level shifter operates only at the high power supply voltage.
摘要翻译： 将低电源电压输入信号转换到较高电源电压输出信号的电平移位器包括第一单元和第二单元。 第一单元连接到高电源电压源并接收输入信号。 第一单元用作启动电路，使得当电平转换器接通时，如果输入信号为逻辑低，则第一单元放电输出节点，并且当输入信号为逻辑高时，第一单元对控制器 节点到输入信号的电压。 第二单元连接到第一单元和高电源电压源，并且还接收输入信号。 第二单元将输入信号移动到较高的电源电压输出信号。 电平转换器仅在高电源电压下工作。
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3.发明授权公开(公告)号：US09065433B2
公开(公告)日：2015-06-23
申请号：US13743323
申请日：2013-01-16
CPC分类号： H03K4/06
摘要： A capacitor charging circuit has input, output and control nodes, first and second series connected primary FETs, and first and second leakage current reduction FETs. All of the FETs have their gates coupled to the control node. The first primary FET is coupled between the input and output nodes, and the second primary FET is coupled between the output node and a leakage current reduction node. The first leakage current reduction FET is coupled between a supply line and the leakage current reduction node, and the second leakage current reduction FET is coupled between the leakage current reduction node and ground. When a control signal at the control node is low, the first primary FET and the first leakage current reduction FET are conductive, and the second primary FET and the second leakage current reduction FET are non-conductive, which eliminates sub-threshold leakage current flowing through the second primary FET.
摘要翻译： 电容充电电路具有输入，输出和控制节点，第一和第二串联连接的主要FET以及第一和第二漏电流减少FET。 所有的FET都具有耦合到控制节点的门。 第一主FET耦合在输入和输出节点之间，第二主要FET耦合在输出节点和漏电流减少节点之间。 第一泄漏电流降低FET耦合在电源线和漏电流减小节点之间，并且第二漏电流减小FET耦合在漏电流减少节点和地之间。 当控制节点处的控制信号为低电平时，第一初级FET和第一漏电流降低FET导通，并且第二初级FET和第二漏电流减小FET不导通，这消除了亚阈值漏电流流动 通过第二个主要FET。
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公开(公告)号：US08390347B1
公开(公告)日：2013-03-05
申请号：US13402844
申请日：2012-02-22
IPC分类号： H03L7/06
CPC分类号： H03L7/1077 , H03L7/085 , H03L7/089
摘要： A phase to digital converter for a digital PLL (Phase Locked Loop) provides an output in the same or single reference clock period for which it is digitizing the phase error information. The phase to digital converter operates on a positive edge of the reference clock and a digital filter operates on the negative edge of the reference clock so the phase correction performed by the PLL occurs in the same reference clock cycle in which the phase to digital converter is digitizing the phase error information.
摘要翻译： 用于数字PLL（锁相环）的相位数字转换器提供在相位或单个参考时钟周期内的输出，为此数字转换器正在数字化相位误差信息。 相位到数字转换器在参考时钟的上升沿工作，数字滤波器在参考时钟的负沿工作，因此PLL执行的相位校正发生在相位到数字转换器的相同参考时钟周期 数字化相位误差信息。
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公开(公告)号：US08253458B2
公开(公告)日：2012-08-28
申请号：US13004043
申请日：2011-01-11
申请人： Anand K. Sinha , Sanjay K. Wadhwa
发明人： Anand K. Sinha , Sanjay K. Wadhwa
IPC分类号： H03L7/06
CPC分类号： H03L7/1075 , H03L2207/50
摘要： A method to operate a digital phase locked loop (DPLL) in which the DPLL includes a phase-frequency detector that compares the frequency of a reference signal with a feedback signal to generate an error signal. The error signal is used to generate first and second control words. Binary current control word bits and thermometric current control word bits are generated using the first and second control words, respectively. A binary controller switches a first set of binary current sources prior to a frequency lock being achieved using the binary current control word bits and the thermometric current control word bits are held at a predetermined value. After achieving the frequency lock, the binary current sources are fixed and then a thermometric controller switches a second set of thermometric current sources using the thermometric current control word bits. Operating the DPLL using the binary controller before the frequency lock and the thermometric controller after the frequency lock reduces switching noise and achieves stable loop dynamics.
摘要翻译： 一种操作数字锁相环（DPLL）的方法，其中DPLL包括将参考信号的频率与反馈信号进行比较以产生误差信号的相位频率检测器。 误差信号用于产生第一和第二控制字。 分别使用第一和第二控制字产生二进制电流控制字位和测温电流控制字位。 二进制控制器在使用二进制电流控制字位实现频率锁定之前切换第一组二进制电流源，并且将测温电流控制字位保持在预定值。 在实现频率锁定之后，二进制电流源是固定的，然后温度控制器使用温度计电流控制字位来切换第二组测温电流源。 频率锁定之前使用二进制控制器操作DPLL，频率锁定后的温度控制器可以降低开关噪声并实现稳定的环路动态。
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公开(公告)号：US08063678B2
公开(公告)日：2011-11-22
申请号：US13109013
申请日：2011-05-17
申请人： Sanjay K. Wadhwa , Krishna Thakur
发明人： Sanjay K. Wadhwa , Krishna Thakur
IPC分类号： H03L7/06
CPC分类号： H03L7/0896
摘要： A charge pump includes a charge pump core circuit having a first current source transistor, a second current source transistor and an output terminal (64), and a replica bias circuit. The replica bias circuit has a first reference current source transistor, a second reference current source transistor and a reference node corresponding to the output terminal of the charge pump core circuit. The reference node is connected to gates of the second current source transistor and the second reference current source transistor. A first input of a regulator circuit is connected to the output terminal of the charge pump core circuit. A second input of the regulator circuit is connected to the reference node of the replica bias circuit. An output of the regulator circuit (54) is connected to gates of the first current source transistor and the first reference current source transistor.
摘要翻译： 电荷泵包括具有第一电流源晶体管，第二电流源晶体管和输出端子（64）的电荷泵芯电路和复制偏置电路。 复制偏置电路具有第一参考电流源晶体管，第二参考电流源晶体管和对应于电荷泵芯电路的输出端的参考节点。 参考节点连接到第二电流源晶体管和第二参考电流源晶体管的栅极。 调节器电路的第一输入端连接到电荷泵芯电路的输出端。 调节器电路的第二输入连接到复制偏置电路的参考节点。 调节器电路（54）的输出端连接到第一电流源晶体管和第一参考电流源晶体管的栅极。
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公开(公告)号：US20100283517A1
公开(公告)日：2010-11-11
申请号：US12436153
申请日：2009-05-06
申请人： Sanjay K. WADHWA , Krishna THAKUR
发明人： Sanjay K. WADHWA , Krishna THAKUR
CPC分类号： H03L7/0896
摘要： A charge pump includes a charge pump core circuit having a first current source transistor, a second current source transistor and an output terminal (64), and a replica bias circuit. The replica bias circuit has a first reference current source transistor, a second reference current source transistor and a reference node corresponding to the output terminal of the charge pump core circuit. The reference node is connected to gates of the second current source transistor and the second reference current source transistor. A first input of a regulator circuit is connected to the output terminal of the charge pump core circuit. A second input of the regulator circuit is connected to the reference node of the replica bias circuit. An output of the regulator circuit (54) is connected to gates of the first current source transistor and the first reference current source transistor.
摘要翻译： 电荷泵包括具有第一电流源晶体管，第二电流源晶体管和输出端子（64）的电荷泵芯电路和复制偏置电路。 复制偏置电路具有第一参考电流源晶体管，第二参考电流源晶体管和对应于电荷泵芯电路的输出端的参考节点。 参考节点连接到第二电流源晶体管和第二参考电流源晶体管的栅极。 调节器电路的第一输入端连接到电荷泵芯电路的输出端。 调节器电路的第二输入连接到复制偏置电路的参考节点。 调节器电路（54）的输出端连接到第一电流源晶体管和第一参考电流源晶体管的栅极。
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公开(公告)号：US07394299B2
公开(公告)日：2008-07-01
申请号：US11538304
申请日：2006-10-03
申请人： Sanjay K. Wadhwa , Deeya Muhury , Pawan K. Tiwari
发明人： Sanjay K. Wadhwa , Deeya Muhury , Pawan K. Tiwari
IPC分类号： H03B19/00
摘要： A digital clock frequency multiplier (100) for increasing an input frequency of an input clock signal includes a generator (102) that receives the input clock signal and a high frequency digital signal. The generator (102) divides a count (Nhf) of a number of cycles of the high frequency digital signal in one period of the input clock signal by a predetermined multiplication factor (MF) for generating an output clock signal. The output clock signal has a predetermined output frequency.
摘要翻译： 用于增加输入时钟信号的输入频率的数字时钟倍频器（100）包括接收输入时钟信号和高频数字信号的发生器（102）。 发生器（102）将输入时钟信号的一个周期中的高频数字信号的周期数的计数（N
Hf ）除以用于产生输出的预定乘法因子（MF） 时钟信号。 输出时钟信号具有预定的输出频率。 -
公开(公告)号：US07084698B2
公开(公告)日：2006-08-01
申请号：US10964793
申请日：2004-10-14
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A band-gap reference circuit for generation of voltages and currents independent of process, voltage, and temperature includes three inversely proportional to absolute temperature (IPTAT) current generators. The IPTAT current generators generate three currents that are added to generate a current independent of the absolute temperature. The generated current is passed through a switched capacitor resistor to generate the band-gap reference voltage across the switched capacitor resistor.
摘要翻译： 用于产生独立于过程，电压和温度的电压和电流的带隙基准电路包括与绝对温度（IPTAT）电流发生器成反比的三个。 IPTAT电流发生器产生三个电流，其被添加以产生独立于绝对温度的电流。 所产生的电流通过开关电容电阻器，以产生开关电容电阻两端的带隙基准电压。
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公开(公告)号：US09225317B1
公开(公告)日：2015-12-29
申请号：US14580144
申请日：2014-12-22
申请人： Sanjay K. Wadhwa , Kulbhushan Misri
发明人： Sanjay K. Wadhwa , Kulbhushan Misri
IPC分类号： H03L5/00 , H03K3/356 , H03K19/003
CPC分类号： H03K19/00315 , H03K19/018521
摘要： A level shifter operates using first and second input signals. When the first and second input signals are in respective first and second states, a first switching element is activated and an output node is pulled toward a first voltage, first pull-down protection and first pull-down switching elements are deactivated, a first protection node is connected to a first bias voltage, second pull-down protection and second pull-down switching elements are activated, and a second protection node is pulled to a second voltage. When the first and second input signals are in respective second and first states, the first switching element is deactivated, the first pull-down protection and first pull-down switching elements are activated, the output node and the first protection node are pulled toward the second voltage, the second pull-down protection and second pull-down switching elements are deactivated, and the second protection node is connected to the first bias voltage.
摘要翻译： 电平移位器使用第一和第二输入信号进行操作。 当第一和第二输入信号处于相应的第一和第二状态时，第一开关元件被激活并且输出节点被拉向第一电压，第一下拉保护和第一下拉开关元件被去激活，第一保护 节点连接到第一偏置电压，第二下拉保护和第二下拉开关元件被激活，并且第二保护节点被拉到第二电压。 当第一和第二输入信号处于相应的第二和第一状态时，第一开关元件被去激活，第一下拉保护和第一下拉开关元件被激活，输出节点和第一保护节点被拉向 第二电压，第二下拉保护和第二下拉开关元件被去激活，并且第二保护节点连接到第一偏置电压。
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