-
公开(公告)号：US08817659B2
公开(公告)日：2014-08-26
申请号：US12975097
申请日：2010-12-21
申请人： Andre Krijn Nieuwland , Jan Staschulat , Elisabeth Francisca Maria Steffens , Hubertus Gerardus Hendrikus Vermeulen
发明人： Andre Krijn Nieuwland , Jan Staschulat , Elisabeth Francisca Maria Steffens , Hubertus Gerardus Hendrikus Vermeulen
CPC分类号： H04L12/40169 , H04L2012/40241 , H04L2012/40273
摘要： Disclosed is a method of switching modes in a serial data communication network comprising a plurality of interconnected nodes, each of said nodes comprising a plurality of mode-dependent configurations, the method including, during a first mode, issuing an instruction to said nodes, said instruction identifying a next mode of the data communication network; terminating said first mode; and following said termination, reconfiguring each of said nodes in accordance with the configuration corresponding to said next mode identified by said instruction. A serial data communication network implementing such a method is also disclosed.
摘要翻译： 公开了一种在包括多个互连节点的串行数据通信网络中切换模式的方法，每个所述节点包括多个依赖于模式的配置，所述方法包括在第一模式期间向所述节点发出指令，所述方法包括： 识别数据通信网络的下一个模式的指令; 终止所述第一模式; 并且在所述终止之后，根据与由所述指令识别的所述下一个模式对应的配置重新配置所述节点。 还公开了实现这种方法的串行数据通信网络。
-
2.发明申请ELECTRONIC DEVICE HAVING LOGIC CIRCUITRY AND METHOD FOR DESIGNING LOGIC CIRCUITRY 审中-公开具有逻辑电路的电子设备和设计逻辑电路的方法公开(公告)号：US20090230988A1
公开(公告)日：2009-09-17
申请号：US11720213
申请日：2005-11-28
IPC分类号： H03K19/007 , G06F17/50
CPC分类号： H03K19/00338 , H03K19/00392
摘要： An electronic device with logic circuitry (LC) is provided. The logic circuitry (LC) comprises at least one electronic unit (EU), in particular one logic gate with a first electronic component (EC1) for performing logic operations; and at least one second electronic component (EC2) for improving the soft-error sensitivity of the logic circuitry (LC). The first and the second electronic component (EC1, EC2) are implemented with substantially the same logical function. The second electronic component (EC2) is redundant. In addition, the inputs of the first and the second electronic component (EC1, E2) are coupled and the outputs of the first and the second electronic component (EC1, E2) are coupled, respectively.
摘要翻译： 提供具有逻辑电路（LC）的电子设备。 逻辑电路（LC）包括至少一个电子单元（EU），特别是具有用于执行逻辑操作的第一电子部件（EC1）的一个逻辑门; 以及用于改善逻辑电路（LC）的软错误灵敏度的至少一个第二电子部件（EC2）。 第一和第二电子部件（EC1，EC2）以基本上相同的逻辑功能实现。 第二电子元件（EC2）是多余的。 另外，第一和第二电子部件（EC1，E2）的输入被耦合，并且第一和第二电子部件（EC1，E2）的输出分别耦合。
-
3.发明申请公开(公告)号：US20080288844A1
公开(公告)日：2008-11-20
申请号：US10598301
申请日：2005-02-23
CPC分类号： G06F11/10 , G06F13/4068
摘要： A module for transmitting sets of data bits to another module via a communication bus using dual-rail encoding is provided that has a reduced switching activity. The module comprises bus invert coding means adapted to compare a set of data bits with a preceding set of data bits to determine an indication of the number of transitions required to transmit the set of data bits; invert the set of data bits prior to transmission if it is determined that the number of transitions required to transmit the set of data bits is greater than half the total number of bits in the set of data bits; and provide an indication of whether the set of data bits has been inverted; the module also comprising means adapted to generate respective copies of the data bits in the set of data bits; and means adapted to transmit to the other module, via the communication bus, the set of data bits, their respective copies and the indication of whether the set of data bits has been inverted.
摘要翻译： 提供了一种用于通过使用双轨编码的通信总线将数据位组发送到另一模块的模块，其具有降低的交换活动。 该模块包括总线反转编码装置，适用于将一组数据比特与前一组数据比特进行比较，以确定发送该组数据比特所需的转换次数的指示; 如果确定发送该组数据位所需的转换次数大于该组数据位中的总位数的一半，则在发送之前反转数据位集合; 并提供该组数据位是否被反转的指示; 该模块还包括适于产生该组数据比特中的数据比特的相应拷贝的装置; 以及适于经由所述通信总线向所述另一个模块发送所述数据位集合，它们各自的副本以及所述数据位组是否已被反转的指示的装置。
-
公开(公告)号：US06615335B1
公开(公告)日：2003-09-02
申请号：US09786292
申请日：2001-03-01
IPC分类号： G06F1200
CPC分类号： H03M7/30 , H04N19/115 , H04N19/124 , H04N19/126 , H04N19/137 , H04N19/15 , H04N19/152 , H04N19/176 , H04N19/18 , H04N19/192 , H04N19/30 , H04N19/60 , Y10S707/99942
摘要： Disclosed is a method of compressing information for storage in a fixed size memory. The data items (D(k)) that constitute the information are divided into pieces (D(s,k)) of decreasing significance. For example, the DCT blocks of an image are hierarchically quantized (3). The memory (5) is organized in corresponding memory layers (501-504). Successive memory layers have a decreasing number of memory locations. Every time a data item is applied to the memory, its less significant data pieces will have to compete with corresponding data pieces of previously stored data items. Depending on its contribution to perceptual image quality, the applied data piece is stored or the stored data piece is kept. Links (511-513, 521-522) are stored in the memory to identify the path along which a data item is stored. Eventually, the image is automatically compressed so as to exactly fit in the memory. FIG. 2.
摘要翻译： 公开了一种压缩信息以便存储在固定大小的存储器中的方法。 构成信息的数据项（D（k））被划分成具有递减意义的（D（s，k））。 例如，图像的DCT块被分层量化（3）。 存储器（5）被组织在相应的存储器层（501-504）中。 连续的存储器层具有减少的存储器位置数量。 每当将数据项应用于存储器时，其较不重要的数据将必须与先前存储的数据项的相应数据段进行竞争。 根据其对感知图像质量的贡献，存储所应用的数据片段或保存所存储的数据片段。 链接（511-513,521-522）存储在存储器中以标识存储数据项的路径。 最终，图像被自动压缩，以便精确地配合在存储器中。 图。 2。
-
公开(公告)号：US08560741B2
公开(公告)日：2013-10-15
申请号：US13120087
申请日：2009-09-22
IPC分类号： G06F3/00
CPC分类号： G06F11/3495 , G06F11/348 , G06F11/349 , H04L43/00
摘要： A data processing system 100 comprising a monitor 120 is provided and corresponding system-on-chip, method for monitoring and computer program product. The data processing system comprises multiple processing devices 104, 106, 116, 116 and a monitor 120. The monitor is configured to monitor characteristics of the data streams 102, 112, occurring among the plurality of data processing devices. The monitor comprises a means to determine whether a system characteristic substantially deviates from an expected system characteristic and to raise an anomaly signal if so. The system characteristic depends on the first characteristic and the second characteristic. In this way the monitor increases robustness by monitoring for problems related to deviations in the relation between multiple data streams.
摘要翻译： 提供了包括监视器120的数据处理系统100和相应的系统级芯片监视方法和计算机程序产品。 数据处理系统包括多个处理设备104,106,116,116和监视器120.监视器被配置为监视在多个数据处理设备之间发生的数据流102,112的特性。 监视器包括一种用于确定系统特性是否显着偏离预期系统特性的装置，如果是，则产生异常信号。 系统特性取决于第一特性和第二特性。 以这种方式，监视器通过监视与多个数据流之间的关系的偏差相关的问题来增强鲁棒性。
-
6.发明申请SYSTEM AND METHOD FOR VERIFYING WHETHER A VEHICLE IS EQUIPPED WITH A FUNCTIONAL ON-BOARD UNIT 有权用于验证车辆是否配有功能板载单元的系统和方法公开(公告)号：US20130201011A1
公开(公告)日：2013-08-08
申请号：US13366852
申请日：2012-02-06
IPC分类号： B60Q1/00
CPC分类号： G07B15/063 , G06Q30/0284 , G08G1/0175
摘要： Various exemplary embodiments relate to a verification system and method for verifying whether a vehicle is equipped with a functional on-board unit (OBU). The system may include a license plate recognition system configured to obtain a license plate number of the vehicle at a first location; a database of license plate numbers and OBU information; a wireless communication system configured to send a trigger message to the OBU using the OBU information, and configured to receive a response from the OBU indicating a location of the OBU; and a verification module configured to determine whether the vehicle is equipped with the OBU. The database may include a correspondence of license plate numbers and OBU information. The verification module may determine that the vehicle is equipped with the OBU if the location reported by the OBU is within a specified distance of the first location.
摘要翻译： 各种示例性实施例涉及用于验证车辆是否配备有功能车载单元（OBU）的验证系统和方法。 该系统可以包括：车牌识别系统，被配置为在第一位置获得车辆的车牌号; 车牌号码和OBU信息数据库; 无线通信系统，被配置为使用所述OBU信息向所述OBU发送触发消息，并且被配置为从所述OBU接收指示所述OBU的位置的响应; 以及验证模块，其被配置为确定所述车辆是否配备有所述OBU。 数据库可以包括牌照号和OBU信息的对应关系。 如果由OBU报告的位置在第一位置的指定距离内，则验证模块可以确定车辆配备有OBU。
-
公开(公告)号：US20110194458A1
公开(公告)日：2011-08-11
申请号：US12975097
申请日：2010-12-21
申请人： Andre Krijn NIEUWLAND , Jan STASCHULAT , Elisabeth Francisca Maria STEFFENS , Hubertus Gerardus Hendrikus VERMEULEN
发明人： Andre Krijn NIEUWLAND , Jan STASCHULAT , Elisabeth Francisca Maria STEFFENS , Hubertus Gerardus Hendrikus VERMEULEN
IPC分类号： H04L12/28
CPC分类号： H04L12/40169 , H04L2012/40241 , H04L2012/40273
摘要： Disclosed is a method of switching modes in a serial data communication network comprising a plurality of interconnected nodes, each of said nodes comprising a plurality of mode-dependent configurations, the method including, during a first mode, issuing an instruction to said nodes, said instruction identifying a next mode of the data communication network; terminating said first mode; and following said termination, reconfiguring each of said nodes in accordance with the configuration corresponding to said next mode identified by said instruction. A serial data communication network implementing such a method is also disclosed.
摘要翻译： 公开了一种在包括多个互连节点的串行数据通信网络中切换模式的方法，每个所述节点包括多个依赖于模式的配置，所述方法包括在第一模式期间向所述节点发出指令，所述方法包括： 识别数据通信网络的下一个模式的指令; 终止所述第一模式; 并且在所述终止之后，根据与由所述指令识别的所述下一个模式对应的配置重新配置所述节点。 还公开了实现这种方法的串行数据通信网络。
-
公开(公告)号：US08560932B2
公开(公告)日：2013-10-15
申请号：US10479089
申请日：2002-05-30
申请人： Richard Petrus Kleihorst , Adrianus Johannes Maria Denissen , Andre Krijn Nieuwland , Nico Frits Benschop
发明人： Richard Petrus Kleihorst , Adrianus Johannes Maria Denissen , Andre Krijn Nieuwland , Nico Frits Benschop
CPC分类号： G01R31/3193 , G01R31/31921
摘要： The subject matter hereof relates to error detection. Various example embodiments for error defection are disclosed. In an example method of error detection in a Module UnderTest (MUT), a parity signal representing the parity of an MUT output is compared to a parity signal representing the parity of an errorless MUT output. In an example system, an Actual Parity Generator provides a parity signal representing the parity of on MUT output, a State Parity Generator provides a parity signal representing the parity of an errorless MUT output, and a comparator compares these two parity signals.
摘要翻译： 其主题涉及错误检测。 公开了用于错误偏离的各种示例实施例。 在模块测试（MUT）中的错误检测的示例方法中，将表示MUT输出的奇偶性的奇偶校验信号与表示无错误MUT输出的奇偶性的奇偶校验信号进行比较。 在示例系统中，实际奇偶校验发生器提供表示MUT输出的奇偶性的奇偶校验信号，状态奇偶校验发生器提供表示无错误MUT输出的奇偶性的奇偶校验信号，比较器比较这两个奇偶校验信号。
-
公开(公告)号：US20120054207A1
公开(公告)日：2012-03-01
申请号：US13190633
申请日：2011-07-26
申请人： Hubertus Gerardus Hendrikus Vermeulen , Jan Staschulat , Andre Krijn Nieuwland , Elisabeth Francisca Maria Steffens
发明人： Hubertus Gerardus Hendrikus Vermeulen , Jan Staschulat , Andre Krijn Nieuwland , Elisabeth Francisca Maria Steffens
IPC分类号： G06F17/30
摘要： The present invention relates to a circuit for sorting a set of data values, the circuit comprising a first set of p+q registers for storing the p+q largest data values of the set of data values including p statistical outliers; a second set of p+q registers for storing the p+q smallest data values of the set of data values including p statistical outliers, wherein p is a non-negative integer and q is a positive integer; a controller coupled to each register in said first and second sets, said controller being arranged to: receive the set of data values and for each data value obtain a comparison result of the data value with the respective data values in each of said registers; and update said registers as a function of said comparison results; the circuit further comprising a data processing circuit coupled to at least the q registers in said first and second sets, which for instance may be used to produce an average value of the data values stored in said q registers in response to the controller. The present invention further relates to a sorting method using such a circuit.
摘要翻译： 本发明涉及一种用于对一组数据值进行排序的电路，该电路包括第一组p + q寄存器，用于存储包括p个统计离群值的数据值集合的p + q个最大数据值; 第二组p + q寄存器，用于存储包括p个统计异常值的数据值集合的p + q个最小数据值，其中p是非负整数，q是正整数; 控制器耦合到所述第一和第二组中的每个寄存器，所述控制器被布置为：接收所述一组数据值，并且对于每个数据值，获得所述数据值与每个所述寄存器中的相应数据值的比较结果; 并根据所述比较结果更新所述寄存器; 所述电路还包括耦合到所述第一和第二组中的至少q个寄存器的数据处理电路，其例如可用于响应于控制器产生存储在所述q个寄存器中的数据值的平均值。 本发明还涉及使用这种电路的排序方法。
-
公开(公告)号：US20100223515A1
公开(公告)日：2010-09-02
申请号：US12063156
申请日：2006-08-09
申请人： Andre Krijn Nieuwland , Sandeepkumar Goel , Erik Jan Marinissen , Hubertus Gerardus Hendrikus Vermeulen , Hendrikus Petrus Elisabeth Vranken
发明人： Andre Krijn Nieuwland , Sandeepkumar Goel , Erik Jan Marinissen , Hubertus Gerardus Hendrikus Vermeulen , Hendrikus Petrus Elisabeth Vranken
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318541 , G01R31/31719
摘要： An integrated circuit (10) comprises a scan chain (14) with parallel inputs and outputs coupled to a functional circuit (12a-c). A scan chain modifying circuit (43, 47, 70a-c) is provided coupled to the scan chain (14). When testing is authorized the scan chain modifying circuit operates in a mode wherein a normal shift path is provided through the scan chain. When testing is not authorized the scan chain modifying circuit (43, 47, 70a-c) operates to effect spontaneous dynamic changes in the shift path, which dynamically vary the length of the shift path between external terminals of the integrated circuit while shifting takes place. In an embodiment the dynamical variations are controlled by a running key comparison. In other embodiments running key comparison is used to disable transfer through the scan chain and/or operation of functional circuits.
摘要翻译： 集成电路（10）包括具有耦合到功能电路（12a-c）的并行输入和输出的扫描链（14）。 提供耦合到扫描链（14）的扫描链修改电路（43,47,70a-c）。 当授权测试时，扫描链修改电路以通过扫描链提供正常移位路径的模式工作。 当测试不被授权时，扫描链修改电路（43,47,70a-c）操作以实现移位路径中的自发动态变化，其在移位期间动态地改变集成电路的外部端子之间的移位路径的长度 。 在一个实施例中，通过运行的密钥比较来控制动态变化。 在其他实施例中，运行密钥比较用于禁止通过扫描链的转移和/或功能电路的操作。
-
-
-
-
-
-
-
-
-
搜索结果
18 条记录 (耗时 0.013 秒)
