公开(公告)号：US5815157A

公开(公告)日：1998-09-29

申请号：US570218

申请日：1995-12-11

申请人： Andrew D. Bowen

发明人： Andrew D. Bowen

IPC分类号： G06T15/04 ,  G09B5/00

CPC分类号： G06T15/04

摘要： An addressing scheme for efficient memory use for storing textures with borders. Memory space is allocated for the texture maps, borders, and submaps equaled to two times the width times the height of the texture map to be stored. The memory space is then divided into a rectangular map space having a left-hand portion and a right-hand portion. Storage is accomplished by storing the main texture map on the left-hand portion of the map space. Submaps are then aligned along the bottom edge of the map space at the right in the right-hand portion. Finally, the borders are stored beginning at the top of the right-side portion of the rectangular space. The four corner edges of the borders are stored below the texel borders in the right-side portion.

摘要翻译： 一种用于存储边框纹理的高效内存使用的寻址方案。 内存空间被分配给纹理贴图，边框和子图，等于宽度乘以要存储的纹理图的高度的两倍。 然后将存储器空间分成具有左手部分和右手部分的矩形地图空间。 通过将主纹理贴图存储在地图空间的左侧部分来实现存储。 然后将子图沿着右侧部分右侧的地图空间的底部边缘对齐。 最后，边框从矩形空间的右侧部分的顶部开始存储。 边框的四个角边缘存储在右侧部分的纹素边界下方。

公开(公告)号：US5367632A

公开(公告)日：1994-11-22

申请号：US969634

申请日：1992-10-30

申请人： Andrew D. Bowen ,  David C. Tannenbaum

发明人： Andrew D. Bowen ,  David C. Tannenbaum

IPC分类号： G06F3/153 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G06F15/62

CPC分类号： G09G5/393

摘要： An implementation of a flexible memory controller for a graphics hardware system that supports flexible allocation of frame buffer resources. The buffer selection and steering to the channels of the modification logic are performed by a programmable controller. Furthermore, the controller is capable of performing pixel functions that require multiple frame buffer accesses per pixel. Still further, independent control is provided for read and write sequences. Also, separate control is provided for buffer selection and bus steering. This function is useful for controlling systems where the frame buffer resources are limited. The present invention allows for assigning various buffers alternate functions based on the application's requirements, and may vary on a per window basis.

摘要翻译： 用于图形硬件系统的灵活存储器控制器的实现，其支持帧缓冲器资源的灵活分配。 通过可编程控制器执行对修改逻辑的通道的缓冲器选择和转向。 此外，控制器能够执行每像素需要多个帧缓冲器访问的像素功能。 此外，为读取和写入序列提供独立的控制。 此外，还提供了用于缓冲​​器选择和总线转向的单独控制。 此功能对于控制帧缓冲区资源有限的系统非常有用。 本发明允许基于应用的要求分配各种缓冲器交替功能，并且可以在每个窗口的基础上变化。

公开(公告)号：US07339590B1

公开(公告)日：2008-03-04

申请号：US10934119

申请日：2004-09-02

申请人： Jeffrey B. Moskal ,  David C. Tannenbaum ,  Andrew D. Bowen ,  Jakob Nebeker

发明人： Jeffrey B. Moskal ,  David C. Tannenbaum ,  Andrew D. Bowen ,  Jakob Nebeker

IPC分类号： G06F15/00 ,  G06T1/00 ,  G06T11/40 ,  G09G5/36

CPC分类号： G06T15/005 ,  G06T1/60 ,  G06T15/80

摘要： A graphics processing subsystem includes a vertex processing unit that allows vertex shader programs to arbitrarily access data stored in vertex texture maps. The vertex processing unit includes a vertex texture fetch unit and vertex processing engines. The vertex processing engines operate in parallel to execute vertex shader programs that specify operations to be performed on vertices. In response to a vertex texture load instruction, a vertex processing engine dispatches a vertex texture request to the vertex texture fetch unit. The vertex texture fetch unit retrieves the corresponding vertex texture map data. While the vertex texture fetch unit is processing a vertex texture request, the requesting vertex processing engine is adapted to evaluate whether instructions that follow the vertex texture load instruction are dependent on the vertex texture map data, and if the instructions are not dependent on the vertex texture map data, to execute the additional instructions.

摘要翻译： 图形处理子系统包括允许顶点着色器程序任意访问存储在顶点纹理图中的数据的顶点处理单元。 顶点处理单元包括顶点纹理提取单元和顶点处理引擎。 顶点处理引擎并行运行以执行指定要对顶点执行的操作的顶点着色器程序。 响应于顶点纹理加载指令，顶点处理引擎向顶点纹理提取单元调度顶点纹理请求。 顶点纹理提取单元检索相应的顶点纹理贴图数据。 当顶点纹理提取单元正在处理顶点纹理请求时，请求顶点处理引擎适于评估跟随顶点纹理加载指令的指令是否取决于顶点纹理贴图数据，并且如果指令不依赖于顶点 纹理贴图数据，执行附加说明。

公开(公告)号：US5434967A

公开(公告)日：1995-07-18

申请号：US967298

申请日：1992-10-27

申请人： David C. Tannenbaum ,  Andrew D. Bowen ,  Robert S. Horton ,  Leland D. Richardson ,  Paul M. Schanely

发明人： David C. Tannenbaum ,  Andrew D. Bowen ,  Robert S. Horton ,  Leland D. Richardson ,  Paul M. Schanely

IPC分类号： G09G5/393 ,  G06F15/16

CPC分类号： G09G5/393

摘要： Hardware logic and processing methods for enhanced data manipulation within a graphics display system are described. The graphics display system includes a graphics processor sub-system and a rendering subsystem which are serially connected for pipeline processing of an interleaved stream of commands and data. One or more status bits or XBITs are defined within each rasterizer of a multi-rasterizer rendering sub-system. An XBIT, which may comprise a ZBIT, a UBIT, or an RBIT, etc., provides a mechanism for introducing execution of various logic functions within the rendering sub-system portion of the computer graphics adapter. Corresponding data processing methods are also described.

摘要翻译： 描述用于在图形显示系统内增强数据操作的硬件逻辑和处理方法。 图形显示系统包括图形处理器子系统和呈现子系统，它们串行连接以用于交错的命令和数据流的流水线处理。 在多光栅化渲染子系统的每个光栅化器内定义一个或多个状态位或XBIT。 可以包括ZBIT，UBIT或RBIT等的XBIT提供用于在计算机图形适配器的渲染子系统部分内引入各种逻辑功能的执行的机制。 还描述了相应的数据处理方法。

公开(公告)号：US07400326B1

公开(公告)日：2008-07-15

申请号：US10944483

申请日：2004-09-16

申请人： Dominic Acocella ,  Robert W. Gimby ,  Thomas H. Kong ,  Andrew D. Bowen ,  Christopher J. Goodman ,  David C. Tannenbaum ,  Jeffrey B. Moskal ,  Steven Gregory Foster, Jr.

发明人： Dominic Acocella ,  Robert W. Gimby ,  Thomas H. Kong ,  Andrew D. Bowen ,  Christopher J. Goodman ,  David C. Tannenbaum ,  Jeffrey B. Moskal ,  Steven Gregory Foster, Jr.

IPC分类号： G06F13/14

CPC分类号： G06F13/4018

摘要： Systems and methods for delivering two data streams via two buses allow one of the buses to be used for delivering selected elements of the data stream that is primarily being delivered by the other bus. At an input rerouting circuit, the selected elements are rerouted from the second data stream into the first data stream; a token inserted in the second data stream identifies a position of the rerouted element. The modified streams are transmitted by the two buses. A receiving circuit reinserts the rerouted data element into the second data stream at the sequential position identified by the placeholder token.

摘要翻译： 通过两个总线传送两个数据流的系统和方法允许一个总线用于传送主要由另一个总线传送的数据流的所选元素。 在输入重路由电路中，所选元素从第二数据流重新路由到第一数据流; 插入第二数据流中的令牌标识重新路由的元素的位置。 修改的流由两条总线传输。 接收电路在由占位符令牌识别的连续位置处将重新路由的数据元素重新插入到第二数据流中。

公开(公告)号：US07292239B1

公开(公告)日：2007-11-06

申请号：US10912930

申请日：2004-08-06

申请人： Henry Packard Moreton ,  Dominic Acocella ,  Robert W. Gimby ,  Thomas M. Ogletree ,  Christopher J. Goodman ,  Andrew D. Bowen ,  David C. Tannenbaum

发明人： Henry Packard Moreton ,  Dominic Acocella ,  Robert W. Gimby ,  Thomas M. Ogletree ,  Christopher J. Goodman ,  Andrew D. Bowen ,  David C. Tannenbaum

IPC分类号： G06T15/00 ,  G06T1/00 ,  G06T1/20 ,  G06F13/00

CPC分类号： G09G5/363 ,  G06T15/40 ,  G09G3/003 ,  G09G5/02 ,  G09G2360/121

摘要： The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within a numerical range limit of the VPC unit. This limitation reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit can cull many primitives despite its culling limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with culling information previously computed for the vertices. To minimize memory bandwidth, the VPC unit retrieves vertex data used for culling operations first. After completing the culling operations, the VPC unit retrieves the attributes of a vertex only if the primitive has not been culled. The VPC unit applies a perspective correction factor to the vertex attributes.

摘要翻译： 图形处理子系统的VPC单元和设置单元执行剔除操作。 VPC单元对属于特定标准的几何图元进行剔除操作，例如具有VPC单元数值范围内的属性。 这种限制降低了VPC单元的复杂性。 随着渲染复杂度的增加，通常会产生大量的小图元，尽管它的淘汰限制，VPC单元也可以剔除许多图元。 VPC单元还包括高速缓存，用于以先前针对顶点计算的剔除信息存储先前处理过的顶点的转换形式。 为了最小化内存带宽，VPC单元首先检索用于剔除操作的顶点数据。 完成剔除操作后，VPC单元仅在原始图元未被剔除时检索顶点的属性。 VPC单元对顶点属性应用透视校正因子。

公开(公告)号：US07233334B1

公开(公告)日：2007-06-19

申请号：US10955779

申请日：2004-09-29

申请人： Dominic Acocella ,  Henry Packard Moreton ,  Robert W. Gimby ,  Thomas H. Kong ,  Andrew D. Bowen

发明人： Dominic Acocella ,  Henry Packard Moreton ,  Robert W. Gimby ,  Thomas H. Kong ,  Andrew D. Bowen

IPC分类号： G06F13/14

CPC分类号： G06F13/4059 ,  Y02D10/14 ,  Y02D10/151

摘要： Accordingly, embodiments of the present invention provide circuits, methods, and apparatus that improve utilization of storage buffers by overwriting data in them as soon as the data is no longer needed. An exemplary embodiment employs a counter to add each time a particular unit of data is needed by a circuit. The counter also subtracts each time the data is actually used by the circuit. When the counter reaches zero, upstream circuitry is checked to see if a command allowing the particular data to be overwritten has been issued. If it has, the command is not waited for, rather the data may be overwritten immediately. Embodiments of the present invention may also make use of one level of indirection to mask physical storage buffer locations from upstream circuitry. In this way, utilization can be improved.

摘要翻译： 因此，本发明的实施例提供了一旦不再需要数据就可以通过覆盖其中的数据来提高存储缓冲器的利用率的电路，方法和装置。 每一次电路需要特定的数据单元时，示例性实施例使用计数器来添加。 每当电路实际使用数据时，计数器也会减去该值。 当计数器达到零时，检查上游电路，看是否允许重写特定数据的命令。 如果有，则不等待命令，而是立即覆盖数据。 本发明的实施例还可以利用一级间接来从上游电路屏蔽物理存储缓冲器位置。 这样可以提高利用率。

公开(公告)号：US06774868B1

公开(公告)日：2004-08-10

申请号：US09232860

申请日：1999-01-15

申请人： Andrew D. Bowen

发明人： Andrew D. Bowen

IPC分类号： G09G500

CPC分类号： G06F3/1446 ,  G09G3/001 ,  G09G3/20 ,  G09G5/393 ,  G09G5/395 ,  G09G2300/026

摘要： A method for tiling multiple displays to generate a large area display of moving data. Specifically, one embodiment of the present invention includes a system for generating a large area display of moving data. The system comprises a display image generator for rendering pixels of an image to be displayed as the large area display. Furthermore, a plurality of tiled image projectors are coupled to the display image generator to receive pixel data and to generate the large area display. The plurality of tiled image projectors comprise at least two image projectors. A first image projector which performs a first type of raster scanning sequence to display a first portion of the pixel data. Moreover, a second image projector which performs a second type of raster scanning sequence to display a second portion of the pixel data, wherein the second type of raster scanning sequence is different than the first type of raster scanning sequence. Therefore, the present invention provides a method and system for tiling multiple image projectors to generate a large area display of moving images and data which is free of visual defects or anomalies. As such, the present invention is able to produce large area displays exhibiting more realistic and lifelike images thereby improving the viewing experience of the viewer.

摘要翻译： 一种用于平铺多个显示器以产生移动数据的大面积显示的方法。 具体地，本发明的一个实施例包括用于产生运动数据的大面积显示的系统。 该系统包括用于渲染图像的像素作为大面积显示的显示图像生成器。 此外，多个平铺图像投影仪耦合到显示图像发生器以接收像素数据并产生大面积显示。 多个平铺图像投影仪包括至少两个图像投影仪。 第一图像投影仪，其执行第一类型的光栅扫描序列以显示像素数据的第一部分。 此外，第二图像投影仪执行第二类型的光栅扫描序列以显示像素数据的第二部分，其中第二类型的光栅扫描序列不同于第一类型的光栅扫描序列。 因此，本发明提供了一种用于平铺多个图像投影仪以产生没有视觉缺陷或异常的运动图像和数据的大面积显示的方法和系统。 因此，本发明能够产生显示更逼真和逼真的图像的大面积显示器，从而改善观看者的观看体验。

公开(公告)号：US5257237A

公开(公告)日：1993-10-26

申请号：US791666

申请日：1991-11-12

申请人： Michael A. Aranda ,  Andrew D. Bowen ,  Timothy J. Ebbers ,  Randall L. Henderson ,  Nathan R. Hiltebeitel ,  Robert Tamlyn

发明人： Michael A. Aranda ,  Andrew D. Bowen ,  Timothy J. Ebbers ,  Randall L. Henderson ,  Nathan R. Hiltebeitel ,  Robert Tamlyn

IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C11/4096

CPC分类号： G11C11/4096 ,  G11C7/1075 ,  G11C8/00

摘要： The selection in a dual port memory device of data from a serial access memory register having a lower byte and an upper byte of data is described herein. In one embodiment, the register is partitioned lengthwise into two sections, corresponding to, for example, a frame buffer A and a frame buffer B. On each serial clock cycle, frame buffer A or frame buffer B for each byte of data may be selected from the register. Each of the selected bytes of data are then passed to a serial output port. In another embodiment, the lower byte of data corresponds to, for example, a frame buffer A and the upper byte corresponds to a frame buffer B. Then either the upper byte or lower byte of data is selected to be output on the serial port. In yet a further embodiment, the serial access memory register is partitioned lengthwise into two sections, each section corresponding to, for example, a frame buffer and the bytes of data correspond to another buffer, then either the lower byte or upper byte is selected to be output on the serial port.

摘要翻译： 这里描述了具有低字节和高字节数​​据的串行访问存储器寄存器的双端口存储器件中的数据的选择。 在一个实施例中，寄存器被纵向分割成对应于例如帧缓冲器A和帧缓冲器B的两个部分。在每个串行时钟周期上，可以选择每个数据字节的帧缓冲器A或帧缓冲器B 从登记册。 然后将每个选定的数据字节传递给串行输出端口。 在另一个实施例中，数据的低字节对应于例如帧缓冲器A，高字节对应于帧缓冲器B.然后选择数据的高字节或低字节在串行端口上输出。 在又一个实施例中，串行访问存储器寄存器被纵向划分为两个部分，每个部分对应于例如帧缓冲器，并且数据字节对应于另一个缓冲器，则低字节或高字节被选择为 在串口上输出。

公开(公告)号：US07400325B1

公开(公告)日：2008-07-15

申请号：US10913667

申请日：2004-08-06

申请人： Robert W. Gimby ,  Henry Packard Moreton ,  Thomas M. Ogletree ,  David C. Tannenbaum ,  Andrew D. Bowen ,  Christopher J. Goodman ,  Vimal Parikh ,  Craig M. Wittenbrink

发明人： Robert W. Gimby ,  Henry Packard Moreton ,  Thomas M. Ogletree ,  David C. Tannenbaum ,  Andrew D. Bowen ,  Christopher J. Goodman ,  Vimal Parikh ,  Craig M. Wittenbrink

IPC分类号： G06T15/40

CPC分类号： G06T15/40 ,  G06T11/40

摘要： The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within of a numerical range limit. This limit reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit culls many primitives despite its limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with previously computed culling information. This increases the VPC unit throughput by reducing the number of memory accesses and culling operations to be performed. The setup unit performs culling operations on any general primitive that cannot be culled by the VPC unit. By performing a first series of culling operations in the VPC unit, the processing burden on the setup unit is decreased.

摘要翻译： 图形处理子系统的VPC单元和设置单元执行剔除操作。 VPC单元对属于特定标准的几何图元执行淘汰操作，例如具有数值范围限制内的属性。 这个限制降低了VPC单元的复杂性。 随着渲染复杂度的增加，通常会产生大量的小图元，尽管存在局限性，但是VPC单元剔除了许多图元。 VPC单元还包括用于以先前计算的剔除信息存储先前处理的顶点的转换形式的高速缓存。 这通过减少要执行的存储器访问和剔除操作的数量来增加VPC单元吞吐量。 设置单元对不能被VPC单元剔除的任何一般原语执行剔除操作。 通过在VPC单元中执行第一系列的淘汰操作，降低了设置单元的处理负担。