公开(公告)号：US5257237A

公开(公告)日：1993-10-26

申请号：US791666

申请日：1991-11-12

申请人： Michael A. Aranda ,  Andrew D. Bowen ,  Timothy J. Ebbers ,  Randall L. Henderson ,  Nathan R. Hiltebeitel ,  Robert Tamlyn

发明人： Michael A. Aranda ,  Andrew D. Bowen ,  Timothy J. Ebbers ,  Randall L. Henderson ,  Nathan R. Hiltebeitel ,  Robert Tamlyn

IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C11/4096

CPC分类号： G11C11/4096 ,  G11C7/1075 ,  G11C8/00

摘要： The selection in a dual port memory device of data from a serial access memory register having a lower byte and an upper byte of data is described herein. In one embodiment, the register is partitioned lengthwise into two sections, corresponding to, for example, a frame buffer A and a frame buffer B. On each serial clock cycle, frame buffer A or frame buffer B for each byte of data may be selected from the register. Each of the selected bytes of data are then passed to a serial output port. In another embodiment, the lower byte of data corresponds to, for example, a frame buffer A and the upper byte corresponds to a frame buffer B. Then either the upper byte or lower byte of data is selected to be output on the serial port. In yet a further embodiment, the serial access memory register is partitioned lengthwise into two sections, each section corresponding to, for example, a frame buffer and the bytes of data correspond to another buffer, then either the lower byte or upper byte is selected to be output on the serial port.

摘要翻译： 这里描述了具有低字节和高字节数​​据的串行访问存储器寄存器的双端口存储器件中的数据的选择。 在一个实施例中，寄存器被纵向分割成对应于例如帧缓冲器A和帧缓冲器B的两个部分。在每个串行时钟周期上，可以选择每个数据字节的帧缓冲器A或帧缓冲器B 从登记册。 然后将每个选定的数据字节传递给串行输出端口。 在另一个实施例中，数据的低字节对应于例如帧缓冲器A，高字节对应于帧缓冲器B.然后选择数据的高字节或低字节在串行端口上输出。 在又一个实施例中，串行访问存储器寄存器被纵向划分为两个部分，每个部分对应于例如帧缓冲器，并且数据字节对应于另一个缓冲器，则低字节或高字节被选择为 在串口上输出。

公开(公告)号：US5001672A

公开(公告)日：1991-03-19

申请号：US352802

申请日：1989-05-16

申请人： Timothy J. Ebbers ,  Satish Gupta ,  Randall L. Henderson ,  Nathan R. Hiltebeitel ,  Robert Tamlyn ,  Steven W. Tomashot ,  Todd Williams

发明人： Timothy J. Ebbers ,  Satish Gupta ,  Randall L. Henderson ,  Nathan R. Hiltebeitel ,  Robert Tamlyn ,  Steven W. Tomashot ,  Todd Williams

IPC分类号： G11C11/401 ,  G11C7/10

CPC分类号： G11C7/1075

摘要： An implementation of a serial access memory register facility which allows the external selection of the portion of the SAM to be scanned out. A control signal is provided which causes the reloading of serial access memory address counter causing the reloading of serial access memory address counter causing the serial scanning to shift from one to another of the serial access memory registers. The result is an ability to select a stopping point when scanning out of the serial access memory. Thus, the present invention implements the ability in a video random access memory to specify both the starting and ending points of the data to be scanned out of the serial access memory. The preferred embodiment replaces the QSF status pin with a control pin to preserve the packaging configuration of standard VRAMs.

公开(公告)号：US5065368A

公开(公告)日：1991-11-12

申请号：US352442

申请日：1989-05-16

申请人： Satish Gupta ,  Randall L. Henderson ,  Nathan R. Hiltebeitel ,  Robert Tamlyn ,  Steven W. Tomashot ,  Todd Williams

发明人： Satish Gupta ,  Randall L. Henderson ,  Nathan R. Hiltebeitel ,  Robert Tamlyn ,  Steven W. Tomashot ,  Todd Williams

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C8/00 ,  G11C11/4096

CPC分类号： G11C11/4096 ,  G11C7/1075 ,  G11C8/00

摘要： An implementation of a serial access memory register that facilitates the selecting from two alternate frame buffers on a per pixel basis. The frame buffers are each stored in a portion of a row in a single video RAM. Following data transfer to the serial access memory register, data from each of the two frame buffers is available. A double buffer select signal controls the selection of which half of the serial access memory register will put data on the output bus for each serial clock signal. The serial clock increments the address pointers in both halves of the serial access memory port simultaneously.

公开(公告)号：US4984214A

公开(公告)日：1991-01-08

申请号：US446032

申请日：1989-12-05

申请人： Nathan R. Hiltebeitel ,  Robert Tamlyn ,  Steven W. Tomashot

发明人： Nathan R. Hiltebeitel ,  Robert Tamlyn ,  Steven W. Tomashot

IPC分类号： G11C11/401 ,  G11C11/4096

CPC分类号： G11C11/4096

摘要： A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells. A first set of mux devices selects one of the two pairs of folded bit lines from each of the arrays, and a second set of mux devices selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

公开(公告)号：US5319606A

公开(公告)日：1994-06-07

申请号：US989688

申请日：1992-12-14

申请人： Andrew D. Bowen ,  Robert Tamlyn

发明人： Andrew D. Bowen ,  Robert Tamlyn

IPC分类号： G11C11/4072 ,  G11C11/408 ,  G11C8/00

CPC分类号： G11C11/408 ,  G11C11/4072

摘要： A dynamic random access memory (DRAM) device that is selectively operable in a normal write mode, in a block write mode, or in a blocked flash write mode in accordance with a mode select signal. In the preferred embodiment, each column of a 512.times.512 DRAM is divided into eight superblocks of 64 columns, each superblock being in turn divided into eight blocks of 8 columns each. An address decoder decodes the most significant column address bits A8-A6 to provide a group select signal specifying a 64-bit superblock, the next most significant column address bits A5-A3 to provide a block select signal specifying a 8-bit block, and the least significant column address bits A2-A0 to provide a cell select signal specifying a particular column. In the normal write mode, data is written to the specified column in the specified block in the specified superblock. In the block write mode, the same data is simultaneously written to selected columns in the specified block in the specified superblock. In the blocked flash write mode, the same data is simultaneously written to selected blocks in the specified superblock. An 8-bit data input line (D7-D0) is used to provide bits that select columns in the block write mode or blocks in the blocked flash write mode.

摘要翻译： 一种动态随机存取存储器（DRAM）装置，其可以根据模式选择信号以正常写入模式，块写入模式或阻塞闪存写入模式选择性地工作。 在优选实施例中，512×512 DRAM的每一列被划分为64列的八个超级块，每个超级块又被分成8列，每个8列。 地址解码器解码最高有效列地址位A8-A6，以提供指定64位超块的组选择信号，下一最高有效列地址位A5-A3提供指定8位块的块选择信号，以及 最低有效列地址位A2-A0以提供指定特定列的单元选择信号。 在正常写入模式下，将数据写入指定的超级块中指定块中指定的列。 在块写入模式下，同一数据同时写入指定超级块中指定块中的选定列。 在阻塞闪存写入模式下，相同的数据被同时写入指定的超级块中的选定块。 8位数据输入线（D7-D0）用于提供在块写入模式下选择列的位或阻塞闪存写入模式下的块。

公开(公告)号：US07203127B1

公开(公告)日：2007-04-10

申请号：US11241601

申请日：2005-09-29

申请人： Robert Tamlyn ,  Joshua Osborne

发明人： Robert Tamlyn ,  Joshua Osborne

IPC分类号： G11C8/00

CPC分类号： G11C7/08 ,  G11C11/4091

摘要： Methods and apparatus for operating a secondary sense amplifier according to different timings. Embodiments of the invention generally provide a secondary sense amplifier configured to dynamically adjust its timing according to a need for data in an output buffer. In one embodiment, the secondary sense amplifier is set (causing data to be driven out) by a signal, SSA_SET, the timing of which is adjusted on the basis of a predefined delay and a need for data at the output buffer.

摘要翻译： 根据不同时序操作次级放大器的方法和装置。 本发明的实施例通常提供一个次级感测放大器，其被配置为根据对输出缓冲器中的数据的需要来动态调整其定时。 在一个实施例中，通过信号SSA_SET来设置辅助感测放大器（使数据被驱出），SSA_SET的定时基于预定义的延迟和对输出缓冲器的数据的需要进行调整。

公开(公告)号：US5901093A

公开(公告)日：1999-05-04

申请号：US464044

申请日：1995-06-05

申请人： Nathan Rafael Hiltebeitel ,  Robert Tamlyn ,  Steven William Tomashot ,  Thomas Walter Wyckoff

发明人： Nathan Rafael Hiltebeitel ,  Robert Tamlyn ,  Steven William Tomashot ,  Thomas Walter Wyckoff

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/808 ,  G11C29/818

摘要： An invention is disclosed which implements bit line redundancy in a memory module, such as a dynamic random access memory (DRAM), in accordance with a block write operation. The block write operation is commonly used in dual port RAMs, sometimes referred to as video random access memories (VRAM). Specifically, a block write operation allows a plurality of bits of data to be written to a plurality of adjacent bit lines defined by a column address. The precise combination of adjacent bit lines selected by the column address is designated by an address mask. The invention provides a memory module with a redundant bit decoder that incorporates an address masking function into the redundant bit decoder during block write operations and also bypasses a masking function during normal read and write operations. This redundant bit decoder allows a single redundant bit line to replace any single defective bit line of the selected group of block write bit lines. It eliminates the need for replacing all the selected bit lines and, thereby, saves silicon area and maximizes the utilization of available redundant bit elements.

摘要翻译： 公开了根据块写入操作在存储器模块（例如动态随机存取存储器（DRAM））中实现位线冗余的发明。 块写操作通常用于双端口RAM，有时称为视频随机存取存储器（VRAM）。 具体地，块写入操作允许将多个数据位写入由列地址定义的多个相邻位线。 由列地址选择的相邻位线的精确组合由地址掩码指定。 本发明提供了一种具有冗余位解码器的存储器模块，其在块写入操作期间将地址掩蔽功能合并到冗余位解码器中，并且在正常读取和写入操作期间绕过掩蔽功能。 该冗余位解码器允许单个冗余位线替代所选择的块写入位线组中的任何单个缺陷位线。 它不需要更换所有选定的位线，从而节省了硅面积并最大限度地利用了可用的冗余位元件。

公开(公告)号：US5490114A

公开(公告)日：1996-02-06

申请号：US362086

申请日：1994-12-22

申请人： Edward Butler ,  Robert B. Goodwin ,  Hemen R. Shah ,  Robert Tamlyn

发明人： Edward Butler ,  Robert B. Goodwin ,  Hemen R. Shah ,  Robert Tamlyn

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1024

摘要： A high performance latch for read and write operations in RAM having a Complimentary Interlock circuit that eliminates the need for external timing to the RAM which might limit its high performance operation. For both read and write operations, the complementary interlock circuit extends a latching signal until valid data appears on the read or write data lines, thus preventing a valid data miss.

摘要翻译： 用于具有免费联锁电路的RAM中的读写操作的高性能锁存器，无需外部定时到RAM，这可能限制其高性能操作。 对于读和写操作，互补互锁电路扩展了锁存信号，直到有效数据出现在读或写数据线上，从而防止有效的数据丢失。

公开(公告)号：US20070070788A1

公开(公告)日：2007-03-29

申请号：US11241601

申请日：2005-09-29

申请人： Robert Tamlyn ,  Joshua Osborne

发明人： Robert Tamlyn ,  Joshua Osborne

IPC分类号： G11C8/00

CPC分类号： G11C7/08 ,  G11C11/4091

摘要： Methods and apparatus for operating a secondary sense amplifier according to different timings. Embodiments of the invention generally provide a secondary sense amplifier configured to dynamically adjust its timing according to a need for data in an output buffer. In one embodiment, the secondary sense amplifier is set (causing data to be driven out) by a signal, SSA_SET, the timing of which is adjusted on the basis of a predefined delay and a need for data at the output buffer.

摘要翻译： 根据不同时序操作次级放大器的方法和装置。 本发明的实施例通常提供一个次级感测放大器，其被配置为根据对输出缓冲器中的数据的需要来动态调整其定时。 在一个实施例中，通过信号SSA_SET来设置辅助感测放大器（使数据被驱出），SSA_SET的定时基于预定义的延迟和对输出缓冲器的数据的需要进行调整。

公开(公告)号：US5606269A

公开(公告)日：1997-02-25

申请号：US548651

申请日：1995-10-26

申请人： Dale E. Pontius ,  Robert Tamlyn

发明人： Dale E. Pontius ,  Robert Tamlyn

IPC分类号： H03K5/1534 ,  H03K19/003

CPC分类号： H03K5/1534

摘要： A circuit for detecting an input signal, the circuit having an input node and an output node, includes a first latch having a set input coupled to the input node, for detecting falling transitions at the input node. A second latch having a set input coupled to the input node, detects rising transitions at the input node. A first logic device, responsive to outputs of the first and second latches, detects that an input signal has been received at both the first and second latches. A second logic device, responsive to a complement output of both the first and second latches, resets both the first and second latches.

摘要翻译： 用于检测输入信号的电路，具有输入节点和输出节点的电路包括具有耦合到输入节点的设置输入的第一锁存器，用于检测输入节点处的下降转换。 具有耦合到输入节点的设置输入的第二锁存器检测输入节点处的上升转变。 响应于第一和第二锁存器的输出的第一逻辑器件检测到在第一和第二锁存器都已经接收到输入信号。 响应于第一和第二锁存器的补码输出的第二逻辑器件复位第一和第二锁存器。