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    Three dimensional (3D) memory device sparing
    1.
    发明授权
    Three dimensional (3D) memory device sparing 有权
    三维（3D）存储设备备用

    公开(公告)号：US08869007B2

    公开(公告)日：2014-10-21

    申请号：US13523091

    申请日：2012-06-14

    申请人： Edgar R. Cordero ,  Anil B. Lingambudi ,  Saravanan Sethuraman ,  Kenneth L. Wright

    发明人： Edgar R. Cordero ,  Anil B. Lingambudi ,  Saravanan Sethuraman ,  Kenneth L. Wright

    IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C29/44 ,  H03M13/05

    CPC分类号： G06F11/1072 ,  G06F11/1048 ,  G11C5/04 ,  G11C11/40 ,  G11C29/4401 ,  G11C29/886 ,  G11C2029/0409 ,  H03M13/05

    摘要： According to one embodiment of the present invention, a method for operating a three dimensional (“3D”) memory device includes detecting, by a memory controller, a first error on the 3D memory device and detecting, by the memory controller, a second error in a first chip in a first rank of the 3D memory device, wherein the first chip has an associated first chip select. The method also includes powering up a second chip in a second rank, sending a command from the memory controller to the 3D memory device to replace the first chip in the first chip select with the second chip and correcting the first error using an error control code.

    摘要翻译： 根据本发明的一个实施例，一种用于操作三维（“3D”）存储器件的方法包括由存储器控制器检测3D存储器件上的第一个错误，并由存储器控制器检测第二个错误 在3D存储器件的第一级中的第一芯片中，其中第一芯片具有相关的第一芯片选择。 该方法还包括对第二级别的第二芯片供电，从存储器控制器向3D存储器件发送命令以将第一芯片中的第一芯片替换为第二芯片，并使用错误控制代码校正第一错误 。

    Cable for high speed data communications
    2.
    发明授权
    Cable for high speed data communications 失效
    电缆用于高速数据通信

    公开(公告)号：US08552291B2

    公开(公告)日：2013-10-08

    申请号：US12786673

    申请日：2010-05-25

    申请人： Anil B. Lingambudi ,  Bhyrav M. Mutnury ,  Nam H. Pham ,  Saravanan Sethuraman

    发明人： Anil B. Lingambudi ,  Bhyrav M. Mutnury ,  Nam H. Pham ,  Saravanan Sethuraman

    IPC分类号： H01B11/02

    CPC分类号： H01B11/203 ,  H01B11/183

    摘要： A cable for high speed data communications that includes a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer. The inner conductors and the dielectric layers are disposed within the cable in parallel with a longitudinal axis of the cable. The cable also includes drain conductors disposed within the cable laterally to the inner conductors adjacent to the dielectric layers along the longitudinal axis of the cable and within thirty degrees of a horizontal axis through the inner conductors. The cable also includes a conductive shield composed of a strip of conductive shield material wrapped in a rotational direction along and about the longitudinal axis around the inner conductors, the dielectric layers, and the drain conductors.

    摘要翻译： 一种用于高速数据通信的电缆，包括由第一电介质层包围的第一内导体和由第二电介质层包围的第二内导体。 内部导体和电介质层与电缆的纵向轴线平行地布置在电缆内。 电缆还包括设置在电缆内的漏极导体，沿着电缆的纵向轴线横向延伸到与电介质层相邻的内部导体，并且在穿过内部导体的水平轴线的30度内。 电缆还包括导电屏蔽，该导电屏蔽由导电屏蔽材料条构成，沿着围绕内部导体，电介质层和漏极导体的纵轴围绕旋转方向缠绕。

    IIMPLEMENTING MEMORY PERFORMANCE MANAGEMENT AND ENHANCED MEMORY RELIABILITY ACCOUNTING FOR THERMAL CONDITIONS
    3.
    发明申请
    IIMPLEMENTING MEMORY PERFORMANCE MANAGEMENT AND ENHANCED MEMORY RELIABILITY ACCOUNTING FOR THERMAL CONDITIONS 有权
    记录性能管理和增强记忆可靠性对热条件的会计处理

    公开(公告)号：US20130138901A1

    公开(公告)日：2013-05-30

    申请号：US13307149

    申请日：2011-11-30

    申请人： Edgar R. Cordero ,  Timothy J. Dell ,  Joab D. Henderson ,  Anil B. Lingambudi ,  Girisankar Paulraj ,  Diyanesh B. Vidyapoornachary

    发明人： Edgar R. Cordero ,  Timothy J. Dell ,  Joab D. Henderson ,  Anil B. Lingambudi ,  Girisankar Paulraj ,  Diyanesh B. Vidyapoornachary

    IPC分类号： G06F12/16

    CPC分类号： G06F11/3037 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/3058 ,  G06F2201/81

    摘要： A method, system and computer program product implement memory performance management and enhanced memory reliability of a computer system accounting for system thermal conditions. When a primary memory temperature reaches an initial temperature threshold, reads are suspended to the primary memory and reads are provided to a mirrored memory in a mirrored memory pair, and writes are provided to both the primary memory and the mirrored memory. If the primary memory temperature reaches a second temperature threshold, write operations to the primary memory are also stopped and the primary memory is turned off with DRAM power saving modes such as self timed refresh (STR), and the reads and writes are limited to the mirrored memory in the mirrored memory pair. When the primary memory temperature decreases to below the initial temperature threshold, coherency is recovered by writing a coherent copy from the mirrored memory to the primary memory.

    摘要翻译： 一种方法，系统和计算机程序产品实现了对系统热条件的计算机系统的存储器性能管理和增强的存储器可靠性。 当主存储器温度达到初始温度阈值时，读取将暂停到主存储器，并将读取提供给镜像存储器对中的镜像存储器，并将写入提供给主存储器和镜像存储器。 如果主存储器温度达到第二温度阈值，则对主存储器的写操作也被停止，并且主存储器通过诸如自定时刷新（STR）的DRAM省电模式被关闭，并且读取和写入被限制为 在镜像存储器对中镜像存储器。 当初级存储器温度降低到低于初始温度阈值时，通过将相干拷贝从镜像存储器写入主存储器来恢复一致性。

    THREE DIMENSIONAL(3D) MEMORY DEVICE SPARING
    6.
    发明申请
    THREE DIMENSIONAL(3D) MEMORY DEVICE SPARING 有权
    三维（3D）存储器件分配

    公开(公告)号：US20130339821A1

    公开(公告)日：2013-12-19

    申请号：US13523195

    申请日：2012-06-14

    申请人： Edgar R. Cordero ,  Anil B. Lingambudi ,  Saravanan Sethuraman ,  Kenneth L. Wright

    发明人： Edgar R. Cordero ,  Anil B. Lingambudi ,  Saravanan Sethuraman ,  Kenneth L. Wright

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G11C29/4401 ,  G06F11/1048 ,  G06F11/1072 ,  G06F11/1666 ,  G06F11/20 ,  G11C7/24 ,  G11C29/70 ,  G11C29/83 ,  G11C2029/0411 ,  H03M13/05

    摘要： According to one embodiment of the present invention, a method for bank sparing in a 3D memory device that includes detecting, by a memory controller, a first error in the 3D memory device and detecting a second error in a first element in a first rank of the 3D memory device, wherein the first element in the first rank has an associated first chip select. The method also includes sending a command to the 3D memory device to set mode registers in a master logic portion of the 3D memory device that enable a second element to receive communications directed to the first element and wherein the second element is in a second rank of the 3D memory device, wherein the first element and second element are each either a bank or a bank group that comprise a plurality of chips.

    摘要翻译： 根据本发明的一个实施例，一种用于在三维存储器件中进行库保存的方法，该方法包括由存储器控制器检测3D存储器件中的第一个误差并检测第一个等级的第一个元件中的第二个误差 3D存储器件，其中第一级中的第一元件具有相关联的第一片选。 该方法还包括向3D存储器设备发送命令以设置3D存储器件的主逻辑部分中的模式寄存器，其使得第二元件能够接收指向第一元件的通信，并且其中第二元件处于第二等级 3D存储器件，其中第一元件和第二元件各自是包括多个芯片的存储体或存储体组。

    Implementing memory performance management and enhanced memory reliability accounting for thermal conditions
    7.
    发明授权
    Implementing memory performance management and enhanced memory reliability accounting for thermal conditions 有权
    实现内存性能管理和增强内存可靠性，以满足热条件

    公开(公告)号：US09442816B2

    公开(公告)日：2016-09-13

    申请号：US13307149

    申请日：2011-11-30

    申请人： Edgar R. Cordero ,  Timothy J. Dell ,  Joab D. Henderson ,  Anil B. Lingambudi ,  Girisankar Paulraj ,  Diyanesh B. Vidyapoornachary

    发明人： Edgar R. Cordero ,  Timothy J. Dell ,  Joab D. Henderson ,  Anil B. Lingambudi ,  Girisankar Paulraj ,  Diyanesh B. Vidyapoornachary

    IPC分类号： G06F13/00 ,  G06F11/30 ,  G06F11/16

    CPC分类号： G06F11/3037 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/3058 ,  G06F2201/81

    摘要： A method, system and computer program product implement memory performance management and enhanced memory reliability of a computer system accounting for system thermal conditions. When a primary memory temperature reaches an initial temperature threshold, reads are suspended to the primary memory and reads are provided to a mirrored memory in a mirrored memory pair, and writes are provided to both the primary memory and the mirrored memory. If the primary memory temperature reaches a second temperature threshold, write operations to the primary memory are also stopped and the primary memory is turned off with DRAM power saving modes such as self timed refresh (STR), and the reads and writes are limited to the mirrored memory in the mirrored memory pair. When the primary memory temperature decreases to below the initial temperature threshold, coherency is recovered by writing a coherent copy from the mirrored memory to the primary memory.

    摘要翻译： 一种方法，系统和计算机程序产品实现了对系统热条件的计算机系统的存储器性能管理和增强的存储器可靠性。 当主存储器温度达到初始温度阈值时，读取将暂停到主存储器，并将读取提供给镜像存储器对中的镜像存储器，并将写入提供给主存储器和镜像存储器。 如果主存储器温度达到第二温度阈值，则对主存储器的写操作也被停止，并且主存储器通过诸如自定时刷新（STR）的DRAM省电模式被关闭，并且读取和写入被限制为 在镜像存储器对中镜像存储器。 当初级存储器温度降低到低于初始温度阈值时，通过将相干拷贝从镜像存储器写入主存储器来恢复一致性。

    Using a buffer to replace failed memory cells in a memory component
    8.
    发明授权
    Using a buffer to replace failed memory cells in a memory component 有权
    使用缓冲区来替换内存组件中的故障内存单元

    公开(公告)号：US09128887B2

    公开(公告)日：2015-09-08

    申请号：US13589487

    申请日：2012-08-20

    申请人： Manoj Dusanapudi ,  Prasanna Jayaraman ,  Anil B. Lingambudi ,  Girisankar Paulraj ,  Saravanan Sethuraman ,  Diyanesh B. Vidyapoornachary

    发明人： Manoj Dusanapudi ,  Prasanna Jayaraman ,  Anil B. Lingambudi ,  Girisankar Paulraj ,  Saravanan Sethuraman ,  Diyanesh B. Vidyapoornachary

    IPC分类号： G06F11/16

    CPC分类号： G06F11/16 ,  G06F11/1666 ,  G06F11/20

    摘要： Methods and data processing systems for using a buffer to replace failed memory cells in a memory component are provided. Embodiments include determining that a first copy of data stored within a plurality of memory cells of a memory component contains one or more errors; in response to determining that the first copy contains one or more errors, determining whether a backup cache within the buffer contains a second copy of the data; and in response to determining that the backup cache contains the second copy of the data, transferring the second copy from the backup cache to a location within an error data queue (EDQ) within the buffer and updating the buffer controller to use the location within the EDQ instead of the plurality of memory cells within the memory component.

    摘要翻译： 提供了用于使用缓冲器来替换存储器组件中的故障存储器单元的方法和数据处理系统。 实施例包括确定存储在存储器组件的多个存储器单元内的数据的第一副本包含一个或多个错误; 响应于确定所述第一副本包含一个或多个错误，确定所述缓冲器内的备份高速缓存是否包含所述数据的第二副本; 并且响应于确定所述备份高速缓存包含所述数据的所述第二副本，将所述第二副本从所述备份高速缓存传送到所述缓冲器内的错误数据队列（EDQ）内的位置，并更新所述缓冲器控制器以使用所述缓冲器控制器内的位置 EDQ而不是存储器组件内的多个存储器单元。

    Three dimensional(3D) memory device sparing
    9.
    发明授权
    Three dimensional(3D) memory device sparing 有权
    三维（3D）存储设备备用

    公开(公告)号：US08874979B2

    公开(公告)日：2014-10-28

    申请号：US13523195

    申请日：2012-06-14

    申请人： Edgar R. Cordero ,  Anil B. Lingambudi ,  Saravanan Sethuraman ,  Kenneth L. Wright

    发明人： Edgar R. Cordero ,  Anil B. Lingambudi ,  Saravanan Sethuraman ,  Kenneth L. Wright

    IPC分类号： G11C29/00 ,  G11C29/44 ,  G06F11/10 ,  H03M13/05

    CPC分类号： G11C29/4401 ,  G06F11/1048 ,  G06F11/1072 ,  G06F11/1666 ,  G06F11/20 ,  G11C7/24 ,  G11C29/70 ,  G11C29/83 ,  G11C2029/0411 ,  H03M13/05

    摘要： According to one embodiment of the present invention, a method for bank sparing in a 3D memory device that includes detecting, by a memory controller, a first error in the 3D memory device and detecting a second error in a first element in a first rank of the 3D memory device, wherein the first element in the first rank has an associated first chip select. The method also includes sending a command to the 3D memory device to set mode registers in a master logic portion of the 3D memory device that enable a second element to receive communications directed to the first element and wherein the second element is in a second rank of the 3D memory device, wherein the first element and second element are each either a bank or a bank group that comprise a plurality of chips.

    摘要翻译： 根据本发明的一个实施例，一种用于在三维存储器件中进行库保存的方法，该方法包括由存储器控制器检测3D存储器件中的第一个误差并检测第一个等级的第一个元件中的第二个误差 3D存储器件，其中第一级中的第一元件具有相关联的第一片选。 该方法还包括向3D存储器设备发送命令以设置3D存储器件的主逻辑部分中的模式寄存器，其使得第二元件能够接收指向第一元件的通信，并且其中第二元件处于第二等级 3D存储器件，其中第一元件和第二元件各自是包括多个芯片的存储体或存储体组。

    Using A Buffer To Replace Failed Memory Cells In A Memory Component
    10.
    发明申请
    Using A Buffer To Replace Failed Memory Cells In A Memory Component 有权
    使用缓冲区替换存储器组件中的故障存储单元

    公开(公告)号：US20140053016A1

    公开(公告)日：2014-02-20

    申请号：US13589487

    申请日：2012-08-20

    申请人： Manoj Dusanapudi ,  Prasanna Jayaraman ,  Anil B. Lingambudi ,  Girisankar Paulraj ,  Saravanan Sethuraman ,  Diyanesh B. Vidyapoornachary

    发明人： Manoj Dusanapudi ,  Prasanna Jayaraman ,  Anil B. Lingambudi ,  Girisankar Paulraj ,  Saravanan Sethuraman ,  Diyanesh B. Vidyapoornachary

    IPC分类号： G06F11/16

    CPC分类号： G06F11/16 ,  G06F11/1666 ,  G06F11/20

    摘要： Methods and data processing systems for using a buffer to replace failed memory cells in a memory component are provided. Embodiments include determining that a first copy of data stored within a plurality of memory cells of a memory component contains one or more errors; in response to determining that the first copy contains one or more errors, determining whether a backup cache within the buffer contains a second copy of the data; and in response to determining that the backup cache contains the second copy of the data, transferring the second copy from the backup cache to a location within an error data queue (EDQ) within the buffer and updating the buffer controller to use the location within the EDQ instead of the plurality of memory cells within the memory component.

    摘要翻译： 提供了用于使用缓冲器来替换存储器组件中的故障存储器单元的方法和数据处理系统。 实施例包括确定存储在存储器组件的多个存储器单元内的数据的第一副本包含一个或多个错误; 响应于确定所述第一副本包含一个或多个错误，确定所述缓冲器内的备份高速缓存是否包含所述数据的第二副本; 并且响应于确定所述备份高速缓存包含所述数据的所述第二副本，将所述第二副本从所述备份高速缓存传送到所述缓冲器内的错误数据队列（EDQ）内的位置，并更新所述缓冲器控制器以使用所述缓冲器控制器内的位置 EDQ而不是存储器组件内的多个存储器单元。