公开(公告)号：US06714029B2

公开(公告)日：2004-03-30

申请号：US10320127

申请日：2002-12-16

申请人： Arti Prasad-Roth

发明人： Arti Prasad-Roth

IPC分类号： G01R3102

CPC分类号： G01R1/0466 ,  G01R1/0483

摘要： In order to test, in particular, BGA (Ball Grid Array) contacts, the free contact pin end is formed as a suction tube in which a reduced pressure that acts on the end area of the free contact pin end can be produced. If the diameter of the suction tube is less than the diameter of the component contact with which contact is to be made, a mechanical and electrical contact can be produced by sucking an approaching component contact onto the end area of the contact pin end, without having to exert pressure on the rear face of the component.

摘要翻译： 为了特别地测试BGA（球栅阵列）接触，自由接触针端形成为可以产生作用在自由接触针端的端部区域上的减压的吸入管。 如果吸入管的直径小于要与其接触的部件接触件的直径，则可以通过将接近的部件接触件吸入接触销端部的端部区域而产生机械和电气接触，而不会具有 以对组件的后表面施加压力。

公开(公告)号：US07061227B2

公开(公告)日：2006-06-13

申请号：US10878681

申请日：2004-06-29

申请人： Thorsten Bucksch ,  Arti Prasad Roth

发明人： Thorsten Bucksch ,  Arti Prasad Roth

IPC分类号： G01R31/02

CPC分类号： G01R31/3191

摘要： A process and device for calibrating a semiconductor component test system includes a first connection, at which a corresponding signal, in particular a calibration signal can be input, and a second and third connection, at which the signal, in particular a calibration signal, can be emitted. The first connection is and/or can be connected via a corresponding line to a first switching apparatus, which is and/or can be connected to the second connection. A second switching apparatus is and/or can be connected to the third connection. Advantageously, the signal is then transferred to the second connection, and barred from the third connection by the first switching apparatus being closed and the second switching apparatus being opened.

摘要翻译： 用于校准半导体部件测试系统的过程和设备包括第一连接，在该第一连接处可以输入相应的信号，特别是校准信号，以及第二和第三连接，在该第二连接处，信号，特别是校准信号可以在该连接 被排出。 第一连接和/或可以经由相应的线路连接到第一开关设备，第一开关设备是和/或可以连接到第二连接。 第二开关装置和/或可以连接到第三连接。 有利地，信号然后被传送到第二连接，并且被第一开关装置关闭并且第二开关装置打开的从第三连接被阻止。

公开(公告)号：US20050273678A1

公开(公告)日：2005-12-08

申请号：US11112000

申请日：2005-04-22

申请人： Stefan Dietrich ,  Arti Prasad-Roth ,  Armin Rettenberger ,  Peter Schroegmeier

发明人： Stefan Dietrich ,  Arti Prasad-Roth ,  Armin Rettenberger ,  Peter Schroegmeier

IPC分类号： G06F19/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/56

CPC分类号： G11C29/56 ,  G11C29/14 ,  G11C29/56012 ,  G11C2029/5602

摘要： Test apparatus for testing an integrated circuit The invention relates to a test apparatus for testing an integrated circuit, particularly a DDR semiconductor memory, having at least one data connection for inputting at least one data signal, at least one DQS control connection for inputting at least one unaltered-frequency DQS signal, a device for phase shifting which is designed to take the unaltered-frequency DQS signal and produce a phase-shifted DQS signal, and a combinational logic device which is connected downstream of the device and which logically combines the unaltered-frequency DQS signal with the phase-shifted DQS signal to produce an altered-frequency DQS signal which has a frequency that is increased compared with the frequency of the unaltered-frequency DQS signal and which is provided for latching the data signals or as a clock signal. The invention also relates to a method for operating a test apparatus of this type.

摘要翻译： 用于测试集成电路的测试装置技术领域本发明涉及一种用于测试集成电路的测试装置，特别是具有用于输入至少一个数据信号的至少一个数据连接的DDR半导体存储器，至少一个用于至少输入的DQS控制连接 一个未改变频率的DQS信号，用于相移的器件，其被设计为采取未改变的DQS信号并产生相移DQS信号;以及组合逻辑器件，其连接在器件的下游，并且逻辑地组合未改变的 具有相移DQS信号的DQS信号产生改变频率的DQS信号，其具有与未改变DQS信号的频率相比增加的频率，并且被提供用于锁存数据信号或作为时钟 信号。 本发明还涉及一种用于操作这种类型的测试装置的方法。