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公开(公告)号：US20050213269A1
公开(公告)日：2005-09-29
申请号：US11092885
申请日：2005-03-29
IPC分类号： G01R19/165 , G11C5/14 , G11C11/4074 , G11C29/00 , G11C29/48 , G11C29/50 , H02H3/00
CPC分类号： G11C5/143 , G01R19/16552 , G11C11/401 , G11C11/4074 , G11C29/1201 , G11C29/48 , G11C29/50 , G11C2029/5004
摘要： An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying an input voltage, which is generated internally from an externally applied supply voltage by a voltage generator circuit. The current generator circuit is connected to an output terminal via an interconnect. A first current flows on the interconnect in a test operating state of the integrated circuit. The current generator circuit generates a first partial current in a first test cycle of a test operating state and a second partial current in a subsequent second test cycle. The partial currents are each superposed on the first current on the interconnect. Consequently, three currents occur at the output terminal during the test operating state. The internally generated input voltage of the current generator circuit is determined from the three currents and the reference voltage.
摘要翻译： 集成电路包括具有用于施加参考电压的第一输入端子的电流发生器电路和用于施加由外部施加的电源电压内部由电压发生器电路产生的输入电压的第二输入端子。 电流发生器电路通过互连连接到输出端子。 在集成电路的测试操作状态下，第一电流在互连上流动。 电流发生器电路在随后的第二测试周期中在测试操作状态的第一测试周期和第二部分电流中产生第一部分电流。 部分电流各自叠加在互连上的第一电流上。 因此，在测试操作状态期间，输出端子发生三个电流。 电流发生器电路的内部产生的输入电压由三个电流和参考电压确定。
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公开(公告)号：US20050289413A1
公开(公告)日：2005-12-29
申请号：US11145192
申请日：2005-06-06
CPC分类号： G11C29/1201 , G11C29/14 , G11C29/38
摘要： An integrated semiconductor memory includes memory cells that store a first data record has at least one datum with a first or second data value and a second data record has at least one datum with the first or second data value. The integrated semiconductor memory has a combination circuit that generates the third data record on the output side from the data records fed to the combination circuit on the input side to ascertain based on the third data record whether the first and second data records have been fed to the combination circuit on the input side. The combination circuit generates the datum of the third data record with the first data value, if the first and second data records were fed to the combination circuit on the input side.
摘要翻译： 集成半导体存储器包括存储第一数据记录的存储器单元具有至少一个具有第一或第二数据值的数据，而第二数据记录具有至少一个具有第一或第二数据值的数据。 集成半导体存储器具有组合电路，其从在输入侧馈送到组合电路的数据记录在输出侧产生第三数据记录，以基于第三数据记录来确定第一和第二数据记录是否被馈送到 输入侧的组合电路。 如果第一和第二数据记录被馈送到输入侧的组合电路，则组合电路产生具有第一数据值的第三数据记录的数据。
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公开(公告)号：US20050218960A1
公开(公告)日：2005-10-06
申请号：US11092963
申请日：2005-03-30
CPC分类号： G11C29/1201 , G01R31/275 , G01R31/2884 , G11C29/48 , G11C29/50 , G11C2029/5002
摘要： An integrated circuit includes a circuit component, a first control circuit and a switchable resistance network. An input voltage is fed to the circuit component on the input side. A control signal generated by the first control circuit is fed to the control terminal of the circuit component. With the switchable resistance network, the first resistance or the second resistance is connected between an output terminal of the circuit component and the output terminal of the integrated circuit to generate a voltage drop between the input side and the output terminal of the circuit component. The integrated circuit makes it possible to generate a current at the output terminal of the circuit component in a manner dependent on the control signal and the voltage dropped between the input side and the output terminal of the circuit component. Families of characteristic curves of transistors of an integrated circuit are determined by the integrated circuit.
摘要翻译： 集成电路包括电路部件，第一控制电路和可切换电阻网络。 输入电压被馈送到输入侧的电路部件。 由第一控制电路产生的控制信号被馈送到电路部件的控制端。 利用可切换电阻网络，第一电阻或第二电阻连接在电路部件的输出端和集成电路的输出端之间，以在电路部件的输入侧和输出端之间产生电压降。 集成电路使得可以以取决于控制信号的方式在电路部件的输出端产生电流以及在电路部件的输入侧和输出端子之间落下的电压。 集成电路的晶体管的特性曲线族由集成电路确定。
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公开(公告)号：US20050225917A1
公开(公告)日：2005-10-13
申请号：US11100617
申请日：2005-04-07
IPC分类号： G11C29/12 , H01L21/66 , H01L23/58 , H01L27/108 , H02H9/04
CPC分类号： G11C29/12005 , G11C29/12
摘要： Integrated semiconductor circuits, in particular, dynamic random access memories include a multiplicity of generator circuits for generating internal voltage levels from an externally applied supply voltage. During testing, the internal voltage levels are altered by the output voltage generated at the output of the generator circuit being adapted to an externally applied test voltage. If the test voltage is outside a tolerance range, the semiconductor circuit maybe destroyed. A protection circuit connected in parallel with the generator circuit limits the output voltage.
摘要翻译： 集成半导体电路，特别是动态随机存取存储器包括用于从外部施加的电源电压产生内部电压电平的多个发生器电路。 在测试期间，内部电压电平由发生器电路输出端产生的输出电压改变为外部施加的测试电压。 如果测试电压超出公差范围，则半导体电路可能被破坏。 与发生器电路并联连接的保护电路限制输出电压。
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公开(公告)号：US20050018507A1
公开(公告)日：2005-01-27
申请号：US10892251
申请日：2004-07-16
IPC分类号： G11C7/10 , G11C7/12 , G11C11/4094 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/109 , G11C7/04 , G11C7/1078 , G11C7/12 , G11C11/4094 , G11C11/4096
摘要： A circuit for controlling an access to an integrated memory includes a command decoder for receiving at least one external command for an access to the memory. An access controller is connected to the command decoder for receiving internal command signals, which are output by the command decoder. In the course of a memory access, the command decoder outputs a precharge command signal for precharging a row of the memory cell array of the integrated memory. A control circuit, which can determine a temperature of the memory, is designed to temporally variably influence the transmission of the precharge command signal of the command decoder to the access controller in a manner dependent on the temperature of the memory. The write recovery time tWR can be retained even for higher operating frequencies of the memory.
摘要翻译： 用于控制对集成存储器的访问的电路包括命令解码器，用于接收至少一个外部命令以访问存储器。 访问控制器连接到命令解码器，用于接收由命令解码器输出的内部命令信号。 在存储器访问的过程中，命令解码器输出用于对集成存储器的存储单元阵列的行进行预充电的预充电命令信号。 可以确定存储器的温度的控制电路被设计为以取决于存储器的温度的方式在时间上可变地影响命令解码器的预充电命令信号到访问控制器的传输。 即使对于存储器的较高工作频率，也可以保留写恢复时间tWR。
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