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公开(公告)号：US12283801B2
公开(公告)日：2025-04-22
申请号：US18340632
申请日：2023-06-23
Inventor： Matthew D. Thoren , John C. Cobb
Abstract: A collet for multiple wire elements is disclosed. In an example, the collet has a body made of a polymeric material and extends along a central axis from a first end to a second end. The body defines a first passageway extending axially through the body, the first passageway in communication with the environment via a first insertion opening extending along an entire length of the first passageway. The body defines a second passageway extending axially through the body and in communication with the environment along an entire length of the second passageway via a second insertion opening, the second passageway spaced circumferentially from the first passageway. When installed, the collet frictionally engages wire elements when a first wire element is seated in the first passageway and a second wire element is seated in the second passageway.
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公开(公告)号：US12270628B1
公开(公告)日：2025-04-08
申请号：US18474817
申请日：2023-09-26
Inventor： Frank R Stolle , Simone B. Bortolami , Larry H Mack
Abstract: A weapon-mountable smart optic comprising: a time reference configured to output a signal comprising a periodically-repeating feature and time metadata and comprising a first oscillator; at least two sensors configured to gather data, each comprising secondary oscillators; and at least one processor in communication with each of the at least two sensors; wherein each of the at least two sensors is in operative communication with the time reference and is configured to associate an edge of the periodically-repeating signal with a time conveyed by the time metadata, and wherein each of the at least two sensors is configured to gather data, associate time metadata with the gathered data, and to send the gathered data with time metadata to the at least one processor, and wherein the at least one processor is configured to fuse the data gathered by each of the at least two sensors.
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公开(公告)号：US20250112606A1
公开(公告)日：2025-04-03
申请号：US18477116
申请日：2023-09-28
Inventor： Gregory S. Notaro
Abstract: A programmable transimpedance amplifiers (TIA) having T-network feedback architectures for achieving varying levels of gain based on a magnitude of an input current signal. TIA includes an operational amplifier (op-amp), a first or T-network feedback architecture that operatively connects with the op-amp at a first input terminal of the op-amp and the output terminal of the op-amp, a second feedback architecture that operatively connects with the op-amp at the first input terminal of the operational amplifier and the output terminal of the operational amplifier, an input voltage source architecture that operatively connects with a second input terminal of the operational amplifier, and at least one controller that operatively connects with each of the first feedback architecture, the second feedback architecture, and the input voltage source architecture to switch specific architectures between operative states and inoperative states to achieve a predetermined fixed output bias voltage from the operational amplifier.
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公开(公告)号：US20250111881A1
公开(公告)日：2025-04-03
申请号：US18477058
申请日：2023-09-28
Inventor： Gary M. Madison , Kevin Grout
IPC: H03K17/687 , H03K17/60 , H03K19/0175
Abstract: A sample and hold amplifier output buffer with the low leakage of metal oxide semiconductor field effect transistors (MOSFET) combined with the linearity and dynamic range of silicon-germanium (SiGe) bipolar junction transistors (BJT). In one aspect, the present disclosure provides a sample and hold amplifier output buffer placing a MOSFET input device between the base and emitter of a high linearity SiGe BJT.
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公开(公告)号：US20250102277A1
公开(公告)日：2025-03-27
申请号：US18474817
申请日：2023-09-26
Inventor： Frank R Stolle , Simone B. Bortolami , Larry H Mack
Abstract: A weapon-mountable smart optic comprising: a time reference configured to output a signal comprising a periodically-repeating feature and time metadata and comprising a first oscillator; at least two sensors configured to gather data, each comprising secondary oscillators; and at least one processor in communication with each of the at least two sensors; wherein each of the at least two sensors is in operative communication with the time reference and is configured to associate an edge of the periodically-repeating signal with a time conveyed by the time metadata, and wherein each of the at least two sensors is configured to gather data, associate time metadata with the gathered data, and to send the gathered data with time metadata to the at least one processor, and wherein the at least one processor is configured to fuse the data gathered by each of the at least two sensors.
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Patent Agency Ranking
公开(公告)号：US12253964B2
公开(公告)日：2025-03-18
申请号：US17841724
申请日：2022-06-16
Inventor： David D. Moser , Daniel L. Stanley , Tate J. Keegan , Sheldon L. Grass , Joshua C. Schabel , Christopher N. Peters
Abstract: A system that includes a plurality of encapsulation blocks having a plurality of digital signal processing (DSP) blocks provided with preconfigured logic functions and a plurality of pacing control networks operatively connected with the plurality of DSP blocks. The system also includes a streaming cross bar operatively connected with each encapsulation block of the plurality of encapsulation blocks. Each encapsulation block of the plurality of encapsulation blocks includes a DSP block of the plurality of DSP blocks and a pacing control network of the plurality of the pacing control networks. Each DSP block of the plurality of DSP blocks is independently and separately connected with the streaming cross bar via the plurality of pacing control networks.
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公开(公告)号：US20250077755A1
公开(公告)日：2025-03-06
申请号：US18456648
申请日：2023-08-28
Inventor： David D. Moser , Daniel L. Stanley , Jane O. Gilliam
IPC: G06F30/343
Abstract: A semiconductor device includes a data port, a programmable logic block for executing a manufacturer test, and a processor operatively coupled to the data port. The processor is configured to assert, in a first modality, a configuration isolation signal to the data port. The data port is configured to be communicatively isolated from the programmable logic block while the configuration isolation signal is asserted. The processor is configured to de-assert, in a second modality, the configuration isolation signal from the data port. The data port is configured to be communicatively coupled to the programmable logic block while the configuration isolation signal is de-asserted. In some examples, the semiconductor device includes a communication interface communicatively coupled to the programmable logic block, wherein the processor is further configured to cause, in the first modality, data to be loaded into the programmable logic block from a first-in-first-out (FIFO) buffer of the communication interface.
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公开(公告)号：US12235367B2
公开(公告)日：2025-02-25
申请号：US17953512
申请日：2022-09-27
Inventor： John E. Acheson , Michael N. Kloos , Nathaniel L. James , Mitchell Dennis
IPC: G01S19/37
Abstract: Techniques are provided for employing an embedded software defined radio (SDR) in a navigation system. A navigation system implementing the techniques according to an embodiment includes a global positioning system (GPS) receiver configured to acquire and track received GPS signals. The system also includes an SDR configured to process received communication signals. The communication signals include timing data. The SDR is further configured to calculate position and navigation data based on a combination of the processed communication signals and the tracked GPS signals provided by the GPS receiver. The system further includes a system timer configured to provide a common time base for use by the GPS receiver and the SDR. The navigation system is implemented in an application specific integrated circuit (ASIC).
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公开(公告)号：US20250062544A1
公开(公告)日：2025-02-20
申请号：US18451393
申请日：2023-08-17
Inventor： Alexander D. Johnson , James F. Fung
Abstract: An antenna assembly includes a first flare arm, a second flare arm located adjacent to the first flare arm, a feed block having an opening therein, a feed slot extending from the opening to an outer periphery of the feed block, and a feed line integral with the feed block as a contiguous unitary component. The first flare arm and the second flare arm are symmetric about the feed block. The feed line can have a first portion integrated into the feed block and a second portion at least partially extending across the feed slot. A method of fabricating an antenna assembly includes additively manufacturing a feed block having a feed slot adjacent to a first flare arm and a second flare arm, and additively manufacturing a feed line having a first portion integral with the feed block, and a second portion at least partially extending across the feed slot.
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公开(公告)号：US12203191B2
公开(公告)日：2025-01-21
申请号：US18073228
申请日：2022-12-01
Inventor： Peter G. Schunemann , Kevin T. Zawilski
Abstract: A method of growing large GaAs or GaP IR window slabs by HVPE, and in embodiments by LP-HVPE, includes obtaining a plurality of thin, single crystal, epitaxial-quality GaAs or GaP wafers, cleaving the wafers into tiles having ultra-flat, atomically smooth, substantially perpendicular edges, and then butting the tiles together to form an HVPE substrate larger than 4 inches for GaP, and larger than 8 inches or even 12 inches for GaAs. Subsequent HVPE growth causes the individual tiles to fuse by optical bonding into a large “tiled” single crystal wafer, while any defects nucleated at the tile boundaries are healed, causing the tiles to merge with themselves and with the slab with no physical boundaries, and no degradation in optical quality. A dopant such as Si can be added to the epitaxial gases during the final HVPE growth stage to produce EMI shielded GaAs windows.
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