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1.发明授权公开(公告)号：US08753901B2
公开(公告)日：2014-06-17
申请号：US13192974
申请日：2011-07-28
申请人： Ertle Werner , Bernd Goller , Michael Horn , Bernd Kothe
发明人： Ertle Werner , Bernd Goller , Michael Horn , Bernd Kothe
CPC分类号： H01L24/06 , H01L22/32 , H01L24/05 , H01L2224/02166 , H01L2224/0392 , H01L2224/04042 , H01L2224/05553 , H01L2224/05624 , H01L2224/48463 , H01L2224/4847 , H01L2224/4943 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01052 , H01L2924/01057 , H01L2924/01068 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.
摘要翻译： 本发明涉及图案化半导体芯片上的接触区域和测试区域的布置。 接触区域和测试区域通过传导网彼此电连接。 而接触区域布置在没有集成电路的部件的第一区域中，测试区域位于半导体芯片的顶侧的第二区域中，该区域具有集成电路的部件。
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2.发明申请公开(公告)号：US20110294238A1
公开(公告)日：2011-12-01
申请号：US13192974
申请日：2011-07-28
申请人： Werner Ertle , Bernd Goller , Michael Horn , Bernd Kothe
发明人： Werner Ertle , Bernd Goller , Michael Horn , Bernd Kothe
IPC分类号： H01L21/66
CPC分类号： H01L24/06 , H01L22/32 , H01L24/05 , H01L2224/02166 , H01L2224/0392 , H01L2224/04042 , H01L2224/05553 , H01L2224/05624 , H01L2224/48463 , H01L2224/4847 , H01L2224/4943 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01052 , H01L2924/01057 , H01L2924/01068 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.
摘要翻译： 本发明涉及图案化半导体芯片上的接触区域和测试区域的布置。 接触区域和测试区域通过传导网彼此电连接。 而接触区域布置在没有集成电路的部件的第一区域中，测试区域位于半导体芯片的顶侧的第二区域中，该区域具有集成电路的部件。
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3.发明授权公开(公告)号：US08044394B2
公开(公告)日：2011-10-25
申请号：US10522502
申请日：2003-07-29
申请人： Werner Ertle , Bernd Goller , Michael Horn , Bernd Kothe
发明人： Werner Ertle , Bernd Goller , Michael Horn , Bernd Kothe
IPC分类号： H01L23/58
CPC分类号： H01L24/06 , H01L22/32 , H01L24/05 , H01L2224/02166 , H01L2224/0392 , H01L2224/04042 , H01L2224/05553 , H01L2224/05624 , H01L2224/48463 , H01L2224/4847 , H01L2224/4943 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01052 , H01L2924/01057 , H01L2924/01068 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.
摘要翻译： 本发明涉及图案化半导体芯片上的接触区域和测试区域的布置。 接触区域和测试区域通过传导网彼此电连接。 而接触区域布置在没有集成电路的部件的第一区域中，测试区域位于半导体芯片的顶侧的第二区域中，该区域具有集成电路的部件。
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4.发明申请公开(公告)号：US20060097386A1
公开(公告)日：2006-05-11
申请号：US10522502
申请日：2003-07-29
申请人： Werner Ertle , Bernd Goller , Michael Horn , Bernd Kothe
发明人： Werner Ertle , Bernd Goller , Michael Horn , Bernd Kothe
IPC分类号： H01L23/34
CPC分类号： H01L24/06 , H01L22/32 , H01L24/05 , H01L2224/02166 , H01L2224/0392 , H01L2224/04042 , H01L2224/05553 , H01L2224/05624 , H01L2224/48463 , H01L2224/4847 , H01L2224/4943 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01052 , H01L2924/01057 , H01L2924/01068 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.
摘要翻译： 本发明涉及图案化半导体芯片上的接触区域和测试区域的布置。 接触区域和测试区域通过传导网彼此电连接。 而接触区域布置在没有集成电路的部件的第一区域中，测试区域位于半导体芯片的顶侧的第二区域中，该区域具有集成电路的部件。
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