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公开(公告)号：US11108325B2
公开(公告)日：2021-08-31
申请号：US16791623
申请日：2020-02-14
摘要： A method including producing an electronic circuit. The method can include providing a first circuit portion, a second circuit portion, a flying capacitor voltage comparator, an output switching circuit, an electronic circuit first output node, and/or an electronic circuit second output node. The electronic circuit first output node can be electrically coupled to a first gate terminal of a switching converter. The electronic circuit second output node can be electrically coupled to a second gate terminal of the switching converter. The method also can include electrically coupling a voltage sensor output terminal of the flying capacitor voltage comparator to the first circuit second input node of the first circuit portion and the second circuit second input node of the second circuit portion. Other embodiments are disclosed.
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2.发明授权Low-to-medium power single chip digital controlled DC-DC regulator for point-of-load applications 有权低至中功率单芯片数字控制DC-DC调节器，用于负载点应用公开(公告)号：US09024606B2
公开(公告)日：2015-05-05
申请号：US13332343
申请日：2011-12-20
申请人： Philippe C. Adell , Bertan Bakkaloglu , Bert Vermeire , Tao Liu
发明人： Philippe C. Adell , Bertan Bakkaloglu , Bert Vermeire , Tao Liu
CPC分类号： H02M3/1588 , H02M2001/0009 , H02M2001/0012 , Y02B70/1466
摘要： A DC-DC converter for generating a DC output voltage includes: a digitally controlled pulse width modulator (DPWM) for controlling a switching power stage to supply a varying voltage to an inductor; and a digital voltage feedback circuit for controlling the DPWM in accordance with a feedback voltage corresponding to the DC output voltage, the digital voltage feedback circuit including: a first voltage controlled oscillator for converting the feedback voltage into a first frequency signal and to supply the first frequency signal to a first frequency discriminator; a second voltage controlled oscillator for converting a reference voltage into a second frequency signal and to supply the second frequency signal to a second frequency discriminator; a digital comparator for comparing digital outputs of the first and second frequency discriminators and for outputting a digital feedback signal; and a controller for controlling the DPWM in accordance with the digital feedback signal.
摘要翻译： 用于产生DC输出电压的DC-DC转换器包括：数字控制脉宽调制器（DPWM），用于控制开关功率级以向电感器提供变化的电压; 以及数字电压反馈电路，用于根据对应于直流输出电压的反馈电压来控制DPWM，所述数字电压反馈电路包括：第一压控振荡器，用于将反馈电压转换为第一频率信号并提供第一 频率信号到第一鉴频器; 第二压控振荡器，用于将参考电压转换为第二频率信号，并将第二频率信号提供给第二频率鉴别器; 数字比较器，用于比较第一和第二鉴频器的数字输出并输出数字反馈信号; 以及用于根据数字反馈信号控制DPWM的控制器。
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3.发明授权Current-steering digital-to-analog converter having a minimum charge injection latch 有权具有最小电荷注入锁存器的电流转向数模转换器公开(公告)号：US06992608B2
公开(公告)日：2006-01-31
申请号：US10823046
申请日：2004-04-13
申请人： Weibiao Zhang , Bertan Bakkaloglu
发明人： Weibiao Zhang , Bertan Bakkaloglu
IPC分类号： H03M1/66
CPC分类号： H03M1/0624 , H03M1/747
摘要： A latch architecture for driving unit current cell of a current-steering digital-to-analog converter (DAC) which reduces the drain-source voltage variation of the output current-source transistors and reduces the coupling of unwanted injection of input digital signals as well as clock signals is presented herein. Moreover, this latch helps to achieve lower glitch during code transition with improved dynamic performance. The latch effectively uses the intrinsic RC delay of most transistors within the latch architecture in order to achieve optimal crossing points of complementary control signals. Unwanted input injection or cross-talk is reduced by introducing transistors (904, 906, 932 and 934) that are off during code transitions without compromising the DAC update speed. Conflicts between currently held and new inputs are avoided in an effort to reduce the harmonic distortion. Furthermore, the distortion as a result of the clock signal fed through each transistor in the first and second subcircuit portions cancel each other.
摘要翻译： 用于驱动电流转向数模转换器（DAC）的单元电流单元的锁存架构，其减小输出电流源晶体管的漏源电压变化，并减少输入数字信号的不期望的注入的耦合 因为这里呈现时钟信号。 此外，该锁存器有助于在代码转换期间实现较低的毛刺，并提高动态性能。 锁存器有效地使用锁存器架构内大多数晶体管的固有RC延迟，以实现互补控制信号的最佳交叉点。 通过引入在代码转换期间关闭而不损害DAC更新速度的晶体管（904,906,932和934）来减少不需要的输入注入或串扰。 为了减少谐波失真，避免了当前持有的和新的输入之间的冲突。 此外，作为通过第一和第二子电路中的每个晶体管馈送的时钟信号的结果的失真彼此抵消。
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公开(公告)号：US09026224B2
公开(公告)日：2015-05-05
申请号：US13264777
申请日：2010-04-21
申请人： Ranu Jung , Kenneth Horch , James J. Abbas , Stephen Phillips , Bertan Bakkaloglu , Seung-Jae Kim
发明人： Ranu Jung , Kenneth Horch , James J. Abbas , Stephen Phillips , Bertan Bakkaloglu , Seung-Jae Kim
CPC分类号： A61F2/68 , A61F2002/6827 , A61F2002/7615 , A61F2002/7625 , A61N1/36014
摘要： Techniques, apparatuses, and systems for interfacing multiple sensors with a biological system can include amplifying signals from respective sensors associated with an external device; modulating the amplified signals based on respective different frequency values; and summing the modulated signals to produce an output signal to stimulate a biological system.
摘要翻译： 用于将多个传感器与生物系统接口的技术，装置和系统可以包括放大与外部设备相关联的各个传感器的信号; 基于相应的不同频率值调制放大的信号; 并将调制信号相加以产生输出信号以刺激生物系统。
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5.发明申请Systems and Methods for Analog to Digital Converter Charge Storage Device Measurement 有权用于模数转换器充电存储器件测量的系统和方法公开(公告)号：US20120112941A1
公开(公告)日：2012-05-10
申请号：US12939486
申请日：2010-11-04
IPC分类号： H03M3/04
CPC分类号： H03M1/124 , G01R31/3658 , H01M10/482 , H03M3/494
摘要： Systems and methods for analog to digital conversion charge storage device measurement are presented. In multi-cell charge storage device monitoring systems, accurate measurement of cell voltages is used for protection of the multi-cell device. The disclosed cell referenced solution converts the cell voltage to a digital representation referenced at the cell voltage. The digital representation referenced to the cell voltage is then level shifted to a ground referenced signal suitable for digital post processing. This processing may be used for fault detection of over-voltage, under-voltage, open cell, and similar fault conditions and cell capacity measurements. An example embodiment implements a sigma delta modulator to perform the signal transformation from analog to digital. The disclosed systems and methods may be differential and stackable for multiple cells.
摘要翻译： 提出了模数转换电荷存储器件测量的系统和方法。 在多单元电荷存储装置监视系统中，使用单元电压的精确测量来保护多单元装置。 所公开的电池参考解决方案将电池电压转换为以电池电压参考的数字表示。 然后将电池电压参考的数字表示电平移位到适合于数字后处理的地参考信号。 该处理可用于过电压，欠压，开放电池以及类似故障条件和电池容量测量的故障检测。 示例性实施例实现了Σ-Δ调制器来执行从模拟到数字的信号变换。 所公开的系统和方法可以是多个小区的差分和可堆叠的。
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公开(公告)号：US07315601B2
公开(公告)日：2008-01-01
申请号：US10387848
申请日：2003-03-13
CPC分类号： H03L7/091 , H03L7/1976
摘要： A sample-and-hold (SAH) phase detector (PD) is clocked in such a way (using a reverse clocking mode) so as to avoid quantization noise increases due to folding that is generally associated with conventional charge pump based phase detectors. The PD is clocked with a clean clock (reference clock), rather than a divided clock. The SAH PD architecture additionally includes an integrated filtering function.
摘要翻译： 采样和保持（SAH）相位检测器（PD）以这种方式（使用反向时钟模式）被计时，以避免由于通常与常规基于电荷泵的相位检测器相关联的折叠引起的量化噪声增加。 PD使用干净的时钟（参考时钟）来计时，而不是分时钟。 SAH PD架构还包括集成滤波功能。
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公开(公告)号：US20200266708A1
公开(公告)日：2020-08-20
申请号：US16791623
申请日：2020-02-14
摘要： A method including producing an electronic circuit. The method can include providing a first circuit portion, a second circuit portion, a flying capacitor voltage comparator, an output switching circuit, an electronic circuit first output node, and/or an electronic circuit second output node. The electronic circuit first output node can be electrically coupled to a first gate terminal of a switching converter. The electronic circuit second output node can be electrically coupled to a second gate terminal of the switching converter. The method also can include electrically coupling a voltage sensor output terminal of the flying capacitor voltage comparator to the first circuit second input node of the first circuit portion and the second circuit second input node of the second circuit portion. Other embodiments are disclosed.
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公开(公告)号：US08436620B2
公开(公告)日：2013-05-07
申请号：US12874911
申请日：2010-09-02
申请人： Gary Lee Stirk , Brian Allen , Umar Jameer Lyles , John Houldsworth , Brian Lum-Shue-Chan , Bertan Bakkaloglu
发明人： Gary Lee Stirk , Brian Allen , Umar Jameer Lyles , John Houldsworth , Brian Lum-Shue-Chan , Bertan Bakkaloglu
IPC分类号： G01N27/416
CPC分类号： G01R19/2503
摘要： Systems and methods are provided for monitoring a voltage. A level shifter is configured to generate a current proportional to the voltage of the battery cell. A delta-sigma modulator is configured to convert the current into a first density modulated bitstream representing the voltage of the battery cell. A first reference source is configured to provide a second density modulated bitstream representing a first threshold voltage. A first comparator is configured to compare the first density modulated bitstream and the second density modulated bitstream.
摘要翻译： 提供了用于监测电压的系统和方法。 电平移位器被配置为产生与电池单元的电压成比例的电流。 Δ-Σ调制器被配置为将电流转换成表示电池单元的电压的第一密度调制比特流。 第一参考源被配置为提供表示第一阈值电压的第二密度调制比特流。 第一比较器被配置为比较第一密度调制比特流和第二密度调制比特流。
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公开(公告)号：US20120056624A1
公开(公告)日：2012-03-08
申请号：US12874911
申请日：2010-09-02
申请人： Gary Lee Stirk , Brian Allen , Umar Jameer Lyles , John Houldsworth , Brian Lum-Shue-Chan , Bertan Bakkaloglu
发明人： Gary Lee Stirk , Brian Allen , Umar Jameer Lyles , John Houldsworth , Brian Lum-Shue-Chan , Bertan Bakkaloglu
IPC分类号： G01N27/416
CPC分类号： G01R19/2503
摘要： Systems and methods are provided for monitoring a voltage. A level shifter is configured to generate a current proportional to the voltage of the battery cell. A delta-sigma modulator is configured to convert the current into a first density modulated bitstream representing the voltage of the battery cell. A first reference source is configured to provide a second density modulated bitstream representing a first threshold voltage. A first comparator is configured to compare the first density modulated bitstream and the second density modulated bitstream.
摘要翻译： 提供了用于监测电压的系统和方法。 电平移位器被配置为产生与电池单元的电压成比例的电流。 Δ-Σ调制器被配置为将电流转换成表示电池单元的电压的第一密度调制比特流。 第一参考源被配置为提供表示第一阈值电压的第二密度调制比特流。 第一比较器被配置为比较第一密度调制比特流和第二密度调制比特流。
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公开(公告)号：US07528754B1
公开(公告)日：2009-05-05
申请号：US11672810
申请日：2007-02-08
申请人： Bertan Bakkaloglu , Sayfe Kiaei , Shahin Taleie
发明人： Bertan Bakkaloglu , Sayfe Kiaei , Shahin Taleie
IPC分类号： H03M3/00
CPC分类号： H03M3/504 , H03M3/41 , H03M7/3028 , H03M7/304
摘要： A noise-shaped direct digital IF to RF DAC (DIF2RF) with embedded up-converter mixer is presented. The digital IF signal is noised shaped by a band-pass ΣΔ modulator with a single bit IF output followed by a semi-digital current-mode IF filter to attenuate out-of-band quantization noise. A current steering DAC combines scaled values of local oscillator (LO) signals as current sources for performing current steering and upconversion in a single cell.
摘要翻译： 提出了一种带嵌入式上变频混频器的噪声形直接数字IF至RF DAC（DIF2RF）。 数字IF信号由具有单位IF输出的带通SigmaDelta调制器形成，然后是半数字电流模式IF滤波器，以衰减带外量化噪声。 电流转向DAC将本地振荡器（LO）信号的缩放值组合为用于在单个单元中执行电流转向和上变频的电流源。
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