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1.发明授权公开(公告)号：US06806780B2
公开(公告)日：2004-10-19
申请号：US10387850
申请日：2003-03-13
IPC分类号： H03L700
CPC分类号： H03C3/0933 , H03C3/0925 , H03L7/1976
摘要： A technique is provided for achieving efficient modulation compensation of a &Sgr;&Dgr; fractional PLL. The parameters of the PLL TF are the gain, Kpll, of the PLL and the time constants associated with the loop filter. A careful design of the PLL allows setting the poles and zeros of the PLL TF to fixed values, independent of process and temperature. The unknown parameters of the system are then reduced to one: the PLL gain, K which is the product of the Voltage Controlled Oscillator (VCO), Phase Detector (PD) and divider gains. One unknown variable can be then determined via a single equation, that can be derived at a single frequency. The measurement of a low frequency modulated single tone, for example, is sufficient to characterize the entire PLL TF.
摘要翻译： 提供了一种用于实现SigmaDelta分数PLL的有效调制补偿的技术。 PLL TF的参数是PLL的增益Kpll和与环路滤波器相关联的时间常数。 PLL的仔细设计允许将PLL TF的极点和零点设置为固定值，与过程和温度无关。 然后将系统的未知参数简化为一个：PLL增益，K是压控振荡器（VCO），相位检测器（PD）和分频器增益的乘积。 可以通过单个方程来确定一个未知变量，这可以在单个频率下得到。 例如，低频调制单音的测量足以表征整个PLL TF。
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公开(公告)号：US07315601B2
公开(公告)日：2008-01-01
申请号：US10387848
申请日：2003-03-13
CPC分类号： H03L7/091 , H03L7/1976
摘要： A sample-and-hold (SAH) phase detector (PD) is clocked in such a way (using a reverse clocking mode) so as to avoid quantization noise increases due to folding that is generally associated with conventional charge pump based phase detectors. The PD is clocked with a clean clock (reference clock), rather than a divided clock. The SAH PD architecture additionally includes an integrated filtering function.
摘要翻译： 采样和保持（SAH）相位检测器（PD）以这种方式（使用反向时钟模式）被计时，以避免由于通常与常规基于电荷泵的相位检测器相关联的折叠引起的量化噪声增加。 PD使用干净的时钟（参考时钟）来计时，而不是分时钟。 SAH PD架构还包括集成滤波功能。
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公开(公告)号：US07440491B2
公开(公告)日：2008-10-21
申请号：US10759480
申请日：2004-01-16
申请人： Jaiganesh Balakrishnan , Anuj Batra , Anand G. Dabak , Abdellatif Bellaouar , Paul H. Fontaine , Michel Frechette , Ranjit Gharpurey , Heng-Chih Lin
发明人： Jaiganesh Balakrishnan , Anuj Batra , Anand G. Dabak , Abdellatif Bellaouar , Paul H. Fontaine , Michel Frechette , Ranjit Gharpurey , Heng-Chih Lin
IPC分类号： H04B1/00
CPC分类号： H04B1/719 , H04B1/71635 , H04B1/71637
摘要： System for ultra-wideband communications providing high data rates over an extended operating range in the presence of interferers. A preferred embodiment comprises an ultra-wideband (UWB) device that makes use of a portion of the UWB frequency range to help provide good performance in the presence of interferers. Additionally, since only a portion of the UWB frequency range is used, multiple devices can simultaneously transmit and receive by using different portions of the UWB frequency range.
摘要翻译： 用于在存在干扰源的情况下在扩展工作范围内提供高数据速率的超宽带通信系统。 优选实施例包括利用UWB频率范围的一部分来帮助在存在干扰源的情况下提供良好性能的超宽带（UWB）设备。 此外，由于仅使用UWB频率范围的一部分，所以多个设备可以通过使用UWB频率范围的不同部分同时发送和接收。
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公开(公告)号：US06856174B1
公开(公告)日：2005-02-15
申请号：US10677105
申请日：2003-10-01
IPC分类号： G01R31/3167 , H03M1/10 , H03M1/68 , H03K17/00
CPC分类号： H03M1/1014 , G01R31/3167 , H03M1/68
摘要： The present invention provides a system for providing high-resolution calibration of a programmable semiconductor component (518). The system calibrates the programmable semiconductor component, within a desired accuracy, to a goal value (802). The system provides a primary DAC function (510) and a supplemental DAC function (512), as well as a control function (506). The control function is utilized to determine a first bit step (806) of the primary DAC function that corresponds to the goal value. The control function then determines a second bit step (810) of the supplemental DAC function that corresponds to the goal value. The bit codes of the first and second bit steps are combined by a summing function (514), to provide a programming control word for the programmable semiconductor component.
摘要翻译： 本发明提供了一种用于提供可编程半导体元件（518）的高分辨率校准的系统。 系统将可编程半导体部件以期望的精度校准到目标值（802）。 该系统提供初级DAC功能（510）和补充DAC功能（512）以及控制功能（506）。 控制功能用于确定与目标值对应的初级DAC功能的第一位步骤（806）。 然后，控制功能确定对应于目标值的补充DAC功能的第二位步骤（810）。 通过加法函数（514）将第一和第二位步骤的位代码组合，以提供可编程半导体部件的编程控制字。
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公开(公告)号：US07151473B2
公开(公告)日：2006-12-19
申请号：US11203717
申请日：2005-08-15
IPC分类号： H03M1/84
摘要： A receiver 100 is provided. The receiver 100 comprises an in-phase analog-to-digital converter 112 operable to detect a saturation condition of the in-phase analog-to-digital converter 112 and to adjust the amplitude of a in-phase signal processed by the in-phase analog-to-digital converter 112 to remove the in-phase analog-to-digital converter 112 from the saturation condition and a in-phase digital filter 114 operable to adjust a gain applied to a digital input to the in-phase digital filter 114 from the in-phase analog-to-digital converter 112, the adjustment of the gain substantially inversely proportional to the adjustment of the amplitude of the in-phase signal processed by the in-phase analog-to-digital converter 112. In an embodiment, the receiver 100 also comprises a quadrature path that is substantially similar to the in-phase path, and the in-phase path and the quadrature path comprise a direct conversion receiver. In an embodiment, the in-phase analog-to-digital converter 112 and the in-phase digital filter 114 comprise an intermediate frequency receiver.
摘要翻译： 提供接收器100。 接收器100包括同相模拟数字转换器112，其可操作以检测同相模数转换器112的饱和状态，并调整由同相模数转换器112处理的同相信号的振幅 模数转换器112以从饱和状态除去同相模数转换器112;以及同相数字滤波器114，其可操作以调整施加到同相数字滤波器114的数字输入的增益 来自同相模数转换器112的增益基本上与由同相模数转换器112处理的同相信号的振幅的调整成反比。 在一个实施例中，接收器100还包括基本上类似于同相路径的正交路径，并且同相路径和正交路径包括直接转换接收器。 在一个实施例中，同相模数转换器112和同相数字滤波器114包括中频接收器。
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公开(公告)号：US08669754B2
公开(公告)日：2014-03-11
申请号：US13081239
申请日：2011-04-06
IPC分类号： G05F3/16
CPC分类号： H04B15/06
摘要： A power supply noise rejection circuit for functional circuits, such as a voltage controlled oscillator (VCO). The power supply noise rejection circuit includes an isolation transistor connected to a voltage supply for providing an output current and voltage substantially free of noise across the full frequency range. A current source, a diode connected reference transistor with resistance means connected between its gate and drain terminals, and a dummy circuit serially connected between the voltage supply and ground generate a bias voltage that is applied to the gate of the isolation transistor. The dummy circuit mimics the DC characteristics of the functional circuit such that the output current tracks with process and temperature variations. The isolation transistor and the reference transistor can have negative threshold voltages, and the circuit can include bleed means for drawing current from the gate of the reference transistor and isolation transistor.
摘要翻译： 用于诸如压控振荡器（VCO）的功能电路的电源噪声抑制电路。 电源噪声抑制电路包括连接到电压源的隔离晶体管，用于在整个频率范围内提供基本上没有噪声的输出电流和电压。 电流源，二极管连接的参考晶体管，其电阻装置连接在其栅极和漏极端子之间，并且串联连接在电压源和地之间的虚拟电路产生施加到隔离晶体管的栅极的偏置电压。 虚拟电路模拟功能电路的DC特性，使得输出电流跟踪过程和温度变化。 隔离晶体管和参考晶体管可以具有负阈值电压，并且该电路可以包括用于从参考晶体管和隔离晶体管的栅极引出电流的放电装置。
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公开(公告)号：US20100029228A1
公开(公告)日：2010-02-04
申请号：US12520518
申请日：2007-12-20
申请人： Alan Holden , Hamid Safiri , Michel J.G.J.P. Frechette , Sherif H.K. Embabi , Abdellatif Bellaouar , Stephen Arnold Devison , Tajinder Manku
发明人： Alan Holden , Hamid Safiri , Michel J.G.J.P. Frechette , Sherif H.K. Embabi , Abdellatif Bellaouar , Stephen Arnold Devison , Tajinder Manku
IPC分类号： H04B1/04
CPC分类号： H03G3/3047
摘要： A power ramping circuit for use in the transmit path of a radio frequency (RF) circuit. The power ramping circuit includes parallel connected transistors used as logarithmic resistor attenuators for adjusting current to a mixer circuit in the transmit path. The parallel connected transistors can be sized differently, and are sequentially turned off to gradually increase the current provided to the mixer circuit. A ramp control circuit controls the parallel connected transistors in response to either an analog signal or a digital signal.
摘要翻译： 一种用于射频（RF）电路的发射路径的功率斜坡电路。 功率斜坡电路包括并联的晶体管，用作对数电阻衰减器，用于调节到发射路径中的混频器电路的电流。 并联连接的晶体管的尺寸可以不同，并被依次关闭，以逐渐增加提供给混频器电路的电流。 斜坡控制电路响应于模拟信号或数字信号来控制并联的晶体管。
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8.发明授权公开(公告)号：US07359684B2
公开(公告)日：2008-04-15
申请号：US10012869
申请日：2001-11-06
CPC分类号： H04B1/26 , H04B1/0475 , H04B2001/0491
摘要： A wireless communication device (UST), comprising an input for receiving baseband data (I, Q) in a first signal having a first frequency. The device also comprises circuitry (681, 682) for increasing the first frequency, to form a second signal having a second frequency, in response to a first frequency reference signal (IF2), and the device comprises circuitry (74) for increasing the second frequency, to form a third signal having a third frequency, in response to a second frequency reference signal (LO2). Lastly, the device comprises an antenna (ATU2) for transmitting the baseband data at a final transmission frequency selected as a band within a predetermined set of frequency bands. With reference to the preceding, the first frequency reference signal and the second frequency reference signal are variable and are selected in response to the final transmission frequency which is a particular band selected as a different band at different times and from the predetermined set of frequency bands.
摘要翻译： 一种无线通信设备（UST），包括用于在具有第一频率的第一信号中接收基带数据（I，Q）的输入。 该装置还包括用于增加第一频率的电路（68 1，68 2 2），以响应于第一频率参考信号形成具有第二频率的第二信号 （IF 2 2），并且该装置包括用于响应于第二频率参考信号（LO 2）而增加第二频率以形成具有第三频率的第三信号的电路（74） ）。 最后，该设备包括用于以选定为预定频带组内的频带的最终传输频率发送基带数据的天线（ATU 2）。 参考前述，第一频率参考信号和第二频率参考信号是可变的，并且是响应于作为在不同时间被选择为不同频带的特定频带的最终发射频率和从预定频带组中选择的 。
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公开(公告)号：US20060055579A1
公开(公告)日：2006-03-16
申请号：US11203717
申请日：2005-08-15
IPC分类号： H03M1/12
摘要： A receiver 100 is provided. The receiver 100 comprises an in-phase analog-to-digital converter 112 operable to detect a saturation condition of the in-phase analog-to-digital converter 112 and to adjust the amplitude of a in-phase signal processed by the in-phase analog-to-digital converter 112 to remove the in-phase analog-to-digital converter 112 from the saturation condition and a in-phase digital filter 114 operable to adjust a gain applied to a digital input to the in-phase digital filter 114 from the in-phase analog-to-digital converter 112, the adjustment of the gain substantially inversely proportional to the adjustment of the amplitude of the in-phase signal processed by the in-phase analog-to-digital converter 112. In an embodiment, the receiver 100 also comprises a quadrature path that is substantially similar to the in-phase path, and the in-phase path and the quadrature path comprise a direct conversion receiver. In an embodiment, the in-phase analog-to-digital converter 112 and the in-phase digital filter 114 comprise an intermediate frequency receiver.
摘要翻译： 提供接收器100。 接收器100包括同相模拟数字转换器112，其可操作以检测同相模数转换器112的饱和状态，并调整由同相模数转换器112处理的同相信号的振幅 模数转换器112以从饱和状态除去同相模数转换器112;以及同相数字滤波器114，其可操作以调整施加到同相数字滤波器114的数字输入的增益 来自同相模数转换器112的增益基本上与由同相模数转换器112处理的同相信号的振幅的调整成反比地成比例。在一个实施例中 接收器100还包括基本上类似于同相路径的正交路径，并且同相路径和正交路径包括直接转换接收器。 在一个实施例中，同相模数转换器112和同相数字滤波器114包括中频接收器。
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10.发明授权Programmable linear-in-dB or linear bias current source and methods to implement current reduction in a PA driver with built-in current steering VGA 有权可编程线性dB或线性偏置电流源以及使用内置电流转向VGA实现PA驱动器电流降低的方法公开(公告)号：US06985028B2
公开(公告)日：2006-01-10
申请号：US10689311
申请日：2003-10-20
申请人： See Taur Lee , Abdellatif Bellaouar
发明人： See Taur Lee , Abdellatif Bellaouar
IPC分类号： G05F3/02
CPC分类号： G05F3/262
摘要： Programmable linear-in-dB or linear bias current source with respect to an input voltage is provided. The linear-in-dB or linear bias current may be clipped at a minimum current level, a maximum current level, or a combination thereof. Preferably, the minimum and maximum current levels are determined by the use of one or more constant current sources. The constant current sources limit the amount of voltage applied to the gates of one or more transistors, which in turn control the output current. The use of the circuit may be used to generate linear or reverse-linear current levels with respect to an input voltage. The output of the current generator may be used as an input to a power-amplifier driver, for example.
摘要翻译： 提供了相对于输入电压的可编程线性dB或线性偏置电流源。 线性dB或线性偏置电流可以以最小电流电平，最大电流电平或其组合进行钳位。 优选地，最小和最大电流水平通过使用一个或多个恒定电流源来确定。 恒定电流源限制施加到一个或多个晶体管的栅极的电压的量，其又控制输出电流。 电路的使用可用于相对于输入电压产生线性或反向线性电流水平。 电流发生器的输出可以例如用作功率放大器驱动器的输入。
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