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    EFFICIENCY OF STATIC CORE TURN-OFF IN A SYSTEM-ON-A-CHIP WITH VARIATION
    1.
    发明申请
    EFFICIENCY OF STATIC CORE TURN-OFF IN A SYSTEM-ON-A-CHIP WITH VARIATION 失效
    静态芯片在带有变化的系统中的关闭效率

    公开(公告)号：US20110172984A1

    公开(公告)日：2011-07-14

    申请号：US12727984

    申请日：2010-03-19

    申请人： Chen-Yong Cher ,  Paul W. Coteus ,  Alan Gara ,  Eren Kursun ,  David P. Paulsen ,  Brian A. Schuelke ,  John E. Sheets, II ,  Shurong Tian

    发明人： Chen-Yong Cher ,  Paul W. Coteus ,  Alan Gara ,  Eren Kursun ,  David P. Paulsen ,  Brian A. Schuelke ,  John E. Sheets, II ,  Shurong Tian

    IPC分类号： G06F9/455

    CPC分类号： G06F1/3203 ,  G06F1/206 ,  G06F1/3237 ,  G06F11/24 ,  Y02D10/128 ,  Y02D10/16

    摘要： A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

    摘要翻译： 一种用于提高多核处理器中的静态核心关断的效率的处理器实现的方法，所述方法包括：通过模拟在多核处理器的设计处进行多核处理器的关断分析 其中所述多核处理器的设计阶段的所述多核处理器的关断分析包括对应于第一多核处理器核的第一输出关闭; 在多核处理器的测试阶段对多核处理器进行关断分析，其中多核处理器的测试阶段的多核处理器的关断分析包括对应于第二多核处理器的第二多输出 核心处理器核心关闭; 比较第一输出和第二输出以确定第一输出是否指相同的磁芯作为第二输出关闭; 如果第一输出和第二输出均指向相同的核来关闭，则输出对应于第一多核处理器核心的第三输出。

    Logical signal output drivers for integrated circuit interconnection
    3.
    发明授权
    Logical signal output drivers for integrated circuit interconnection 失效
    用于集成电路互连的逻辑信号输出驱动器

    公开(公告)号：US5287527A

    公开(公告)日：1994-02-15

    申请号：US997380

    申请日：1992-12-28

    申请人： Gary S. Delp ,  Brian A. Schuelke

    发明人： Gary S. Delp ,  Brian A. Schuelke

    IPC分类号： H03K17/693 ,  G06F12/06 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  H03K19/003 ,  H03K19/0175 ,  G11C8/00

    CPC分类号： G11C7/1051 ,  G11C8/12

    摘要： Disclosed is a logic output signal generating integrated circuit having a plurality of output drivers connected in parallel between a power bus and a ground bus. Each output driver has a pull up device disposed between the power bus and an output terminal and a pull down device disposed between the output terminal and the ground bus. Output drivers are paired for the reception of control signals. Control gates to the pull up device and the pull down device for one output driver in a pair is connected to receive an on-chip logic signal. The second output driver of the pair has the complement of that logic signal applied to the control gates of its pull up and pull down devices. An inverter operates on the logic signal to provide the complement. The load is divided between the output drivers for the true signals and those for the complementary signals.

    摘要翻译： 公开了一种逻辑输出信号产生集成电路，其具有并联连接在电源总线和接地总线之间的多个输出驱动器。 每个输出驱动器具有设置在电源总线和输出端子之间的上拉装置和设置在输出端子和接地总线之间的下拉装置。 输出驱动器配对用于接收控制信号。 一对输出驱动器的上拉装置和下拉装置的控制栅极被连接以接收片上逻辑信号。 该对的第二输出驱动器具有施加到其上拉和下拉器件的控制栅极的该逻辑信号的补码。 逆变器对逻辑信号进行操作以提供补码。 负载在真实信号的输出驱动器和互补信号的输出驱动器之间划分。

    Efficiency of static core turn-off in a system-on-a-chip with variation
    5.
    发明授权
    Efficiency of static core turn-off in a system-on-a-chip with variation 失效
    在具有变化的片上系统中静态磁芯关断的效率

    公开(公告)号：US08571847B2

    公开(公告)日：2013-10-29

    申请号：US12727984

    申请日：2010-03-19

    申请人： Chen-Yong Cher ,  Paul W. Coteus ,  Alan Gara ,  Eren Kursun ,  David P. Paulsen ,  Brian A. Schuelke ,  John E. Sheets, II ,  Shurong Tian

    发明人： Chen-Yong Cher ,  Paul W. Coteus ,  Alan Gara ,  Eren Kursun ,  David P. Paulsen ,  Brian A. Schuelke ,  John E. Sheets, II ,  Shurong Tian

    IPC分类号： G06G7/75

    CPC分类号： G06F1/3203 ,  G06F1/206 ,  G06F1/3237 ,  G06F11/24 ,  Y02D10/128 ,  Y02D10/16

    摘要： A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

    摘要翻译： 一种用于提高多核处理器中的静态核心关断的效率的处理器实现的方法，所述方法包括：通过模拟在多核处理器的设计处进行多核处理器的关断分析 其中所述多核处理器的设计阶段的所述多核处理器的关断分析包括对应于第一多核处理器核的第一输出关闭; 在多核处理器的测试阶段对多核处理器进行关断分析，其中多核处理器的测试阶段的多核处理器的关断分析包括对应于第二多核处理器的第二多输出 核心处理器核心关闭; 比较第一输出和第二输出以确定第一输出是否指相同的磁芯作为第二输出关闭; 如果第一输出和第二输出均指向相同的核来关闭，则输出对应于第一多核处理器核心的第三输出。